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path: root/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
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2025-04-11phy: qcom-qmp-ufs: check for mode type for phy settingNitin Rawat
Generally all target supports Rate B but for very few like SM8550, two sets of UFS PHY settings are provided, one set is to support HS-G5 Rate A and another set is to support HS-G4 and lower gears with Rate B. Commit b02cc9a17679("phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750") apply Rate B setting for SM8550 gear 5 without checking for mode value (Rate A or Rate B) from Controller driver which caused issue as SM8550 support rate A for Gear 5. Fix this by adding mode check before applying Rat B phy setting. Fixes: b02cc9a17679 ("phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750") Reported-by: Neil Armstrong <neil.armstrong@linaro.org> Closes: https://lore.kernel.org/all/430ed11c-0490-45be-897b-27cad9682371@quicinc.com/ Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20250407121008.22230-1-quic_nitirawa@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750Nitin Rawat
Add SM8750 specific register layout and table configs. The serdes TX RX register offset has changed for SM8750 and hence keep UFS specific serdes offsets in a dedicated header file. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20250310-sm8750_ufs_master-v2-2-0dfdd6823161@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-31phy: qcom: qmp: Add debug prints for register writesManivannan Sadhasivam
These register prints are useful to validate the init sequence against the Qcom internal documentation and also to share with the Qcom hw engineers to debug issues related to PHY. Sample debug prints: qcom-qmp-pcie-phy 1c0e000.phy: Writing Reg: QSERDES_V5_COM_SYSCLK_EN_SEL Offset: 0x0094 Val: 0xd9 qcom-qmp-pcie-phy 1c0e000.phy: Writing Reg: QSERDES_V5_COM_HSCLK_SEL Offset: 0x0158 Val: 0x11 Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240731152548.102987-1-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-12phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5Neil Armstrong
Update the SM8650 UFS PHY init tables to support Gear 4 and Gear 5 using the overlays setup (only supported Gear 5 before), and sync back with the latest Qualcomm recommended values. The new recommended values allow a solid 50% bump in sequential read/write benchmarks on the SM8650 QRD & HDK reference boards. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240410-topic-sm8650-upstream-ufs-g5-v1-1-5527c44b37e6@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-03-29phy: qcom-qmp-ufs: Add SM8475 supportDanila Tikhonov
Add the tables and constants for init sequences for UFS QMP phy found in SM8475 SoC. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240327180642.20146-3-danila@jiaxyga.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-07phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() APIManivannan Sadhasivam
Device drivers should just rely on the clocks provided by the devicetree and enable/disable them based on the requirement. There is no need to validate the clocks provided by devicetree in the driver. That's the job of DT schema. So let's switch to devm_clk_bulk_get_all() API that just gets the clocks provided by devicetree and remove hardcoded clocks info. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-2-58a49d2f4605@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-30phy: qcom: qmp: move common bits definitions to common headerDmitry Baryshkov
Move bit definitions for the common headers to the common phy-qcom-qmp.h header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-5-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-30phy: qcom: qmp: move common functions to common headerDmitry Baryshkov
Move common init tables code to the common header phy-qcom-qmp-common.h. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-3-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-23phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550Can Guo
On SM8550, two sets of UFS PHY settings are provided, one set is to support HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY settings are programming different values to different registers, mixing the two sets and/or overwriting one set with another set is definitely not blessed by UFS PHY designers. To add HS-G5 support for SM8550, split the two sets of PHY settings into their dedicated overlay tables, only the common parts of the two sets of PHY settings are left in the .tbls. Consider we are going to add even higher gear support in future, to avoid adding more tables with different names, rename the .tbls_hs_g4 and make it an array, a size of 2 is enough as of now. In this case, .tbls alone is not a complete set of PHY settings, so either tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the .tbls to become a complete set of PHY settings. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Can Guo <quic_cang@quicinc.com> Link: https://lore.kernel.org/r/1703557892-1822-1-git-send-email-quic_cang@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-23phy: qcom: qmp-ufs: Add SC7180 supportDavid Wronek
The SC7180 UFS PHY is identical to the one found on SM7150. Add a compatible for it. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: David Wronek <davidwronek@gmail.com> Link: https://lore.kernel.org/r/20240121-sm7125-upstream-v4-5-f7d1212c8ebb@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY SettingsCan Guo
The registers, which are being touched in current SM8550 UFS PHY settings, and the values being programmed are mainly the ones working for HS-G4 mode, meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings. However, even consider HS-G4 mode only, some of them are incorrect and some are missing. Rectify the HS-G4 PHY settings by strictly aligning with the SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings. Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Can Guo <quic_cang@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Link: https://lore.kernel.org/r/1701520577-31163-10-git-send-email-quic_cang@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-16phy: qcom: qmp-ufs: add QMP UFS PHY tables for SM8650Neil Armstrong
Add QMP UFS PHY support for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-5-a543a4c4b491@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280Nitin Rawat
Add SC7280 specific register layout and table configs. Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230918205037.25658-3-quic_nitirawa@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-11phy: qcom: qmp-ufs: add missing offsets to sm8150 configurationDmitry Baryshkov
The conversion commit 7559e7572c03 ("phy: Explicitly include correct DT includes") misses offsets configuration for sm8150 (most likely it was developed separately from the series adding HS G4 support and was not adapted for the sm8150/sm8250 configuration split). Add missing offsets to sm8150_ufsphy_cfg. Fixes: 7559e7572c03 ("phy: Explicitly include correct DT includes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230731111009.3998089-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-17phy: Explicitly include correct DT includesRob Herring
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom-qmp-ufs: populate offsets configurationDmitry Baryshkov
Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230711145153.4167820-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-04-12phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775pBartosz Golaszewski
Add QMP PHY config for sa8775p and add support for the new compatible. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20230411130446.401440-4-brgl@bgdev.pl Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-31phy: qcom-qmp-ufs: Add SM7150 supportDavid Wronek
Add the tables and constants for init sequences for UFS QMP phy found in SM7150 SoC. Signed-off-by: David Wronek <davidwronek@gmail.com> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230311231733.141806-3-danila@jiaxyga.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02phy: qcom-qmp-ufs: Add SM8550 supportAbel Vesa
Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230117224148.1914627-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02phy: qcom-qmp: pcs-ufs: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230117224148.1914627-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-02phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230117224148.1914627-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-18phy: qualcomm: qmp-ufs: rename qmp_ufs_offsets_v5 to qmp_ufs_offsetsDmitry Baryshkov
All currently known QMP UFS PHYs have the same offsets for register sub-regions. Instead of using qmp_ufs_offsets_v5 for older generations of PHYs, rename the offsets struct instance to remove _v5 suffix. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113195515.407866-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoCManivannan Sadhasivam
UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-13-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoCManivannan Sadhasivam
UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-12-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoCManivannan Sadhasivam
UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-11-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Avoid setting HS G3 specific registersManivannan Sadhasivam
SM8350 default init sequence sets some PCS registers to HS G3, thereby disabling HS G4 mode. This has the effect on MPHY capability negotiation between the host and the device during link startup and causes the PA_MAXHSGEAR to G3 irrespective of device max gear. Due to that, the agreed gear speed determined by the UFS core will become G3 only and the platform won't run at G4. So, let's remove setting these registers for SM8350 as like other G4 compatible platforms. One downside of this is that, when the board design uses non-G4 compatible device, then MPHY will continue to run in the default mode (G4) even if UFSHCD runs in G3. But this is the case for other platforms as well. Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-10-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoCManivannan Sadhasivam
UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-9-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoCManivannan Sadhasivam
UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-8-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_bManivannan Sadhasivam
Since now there is support for configuring the HS Rate B mode properly, let's move the register setting to tbls_hs_b struct for all SoCs. This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-7-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 modeManivannan Sadhasivam
Add separate tables_hs_g4 instance to allow the PHY driver to configure the PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and PCS register setting in tables_hs_g4 and the UFS driver can request the Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-6-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B modeManivannan Sadhasivam
Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-5-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls structManivannan Sadhasivam
As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tbls. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-4-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Rename MSM8996 PHY definitionsManivannan Sadhasivam
Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's rename all of the definitions to use "_ufsphy_". Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-17phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitionsManivannan Sadhasivam
Following the other QMP PHY drivers like PCIe, let's remove the "_tbl" suffix from the qmp_phy_init_tbl definitions. This helps in maintaining the uniformity across all of the QMP PHY drivers. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-2-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-13phy: qcom-qmp: Add SM6125 UFS PHY supportLux Aliaga
The SM6125 UFS PHY is compatible with the one from SM6115. Add a compatible for it and modify the config from SM6115 to make them compatible with the SC8280XP binding Signed-off-by: Lux Aliaga <they@mint.lgbt> Reviewed-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20230108195336.388349-4-they@mint.lgbt Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp: move type-specific headers to particular driverDmitry Baryshkov
Remove QMP PHY type-specific headers inclusion from the common header and move them to the specific PHY drivers to cleanup the namespaces used by different drivers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-14-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp-ufs: rename regs layout arraysDmitry Baryshkov
Rename regs layouts to follow the QMP PHY version. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-9-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp-ufs: rework regs layout arraysDmitry Baryshkov
Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-8-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp-ufs: split UFS-specific v2 PCS registers to a separate headerDmitry Baryshkov
Follow other QMP headers, split and rename UFS-specific PCS registers to ease comparing regs differences. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-7-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-01-12phy: qcom-qmp-ufs: provide symbol clocksDmitry Baryshkov
Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src, ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock provider to let other devices link these clocks through the DT. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221123104443.3415267-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-24phy: qcom-qmp: drop unused type headerJohan Hovold
The PHY type defines are no longer used in the PCIe, UFS and USB QMP drivers so drop the corresponding include. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221111094239.11547-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-ufs: add support for updated sc8280xp bindingJohan Hovold
Add support for the new SC8280XP binding. Note that the binding does not try to describe every register subregion and instead the driver holds the corresponding offsets. Also note that the driver will continue to accept the old binding, at least for the time being. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221024090041.19574-11-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-ufs: restructure PHY creationJohan Hovold
In preparation for supporting devicetree bindings which do not use a child node, move the PHY creation to probe() proper and parse the serdes resource in what is now the legacy devicetree helper. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221024090041.19574-10-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-ufs: clean up PHY initJohan Hovold
Clean up the PHY initialisation somewhat programming both tx and rx for the second lane after the first lane. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221024090041.19574-7-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-ufs: rename PHY ops structureJohan Hovold
Rename the PHY operation structure so that it has a "phy_ops" suffix and move it next to the implementation. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221024090041.19574-6-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-ufs: clean up probe initialisationJohan Hovold
Stop abusing the driver data pointer and instead pass the driver state structure directly to the initialisation helpers during probe. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221024090041.19574-5-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-ufs: clean up device-tree parsingJohan Hovold
Since the QMP driver split there will be at most a single child node so drop the obsolete iteration construct. While at it, drop the verbose error logging that would have been printed also on probe deferrals. Note that there's no need to check if there are additional child nodes (the kernel is not a devicetree validator), but let's return an error if there are no child nodes at all for now. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221024090041.19574-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-ufs: merge driver dataJohan Hovold
The UFS QMP PHY driver only manages a single PHY so merge the old qcom_qmp and qmp_phy structures and drop the PHY array. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221024090041.19574-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-ufs: move device-id tableJohan Hovold
Move the device-id table below probe() and next to the driver structure to keep the driver callback functions grouped together. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221024090041.19574-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28phy: qcom-qmp-ufs: drop start and pwrdn-ctrl abstractionJohan Hovold
Drop the start and pwrdn-ctrl abstractions which are no longer needed since the QMP driver split. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221012085002.24099-19-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-30 07:17:28 +0000