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path: root/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c
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2020-01-15drm/nouveau/secboot: move code to boot LS falcons to subdevsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn/msgq: pass explicit message queue pointer to recv()Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn/msgq: move handling of init message to subdevsBen Skeggs
When the PMU/SEC2 LS FWs have booted, they'll send a message to the host with various information, including the configuration of message/command queues that are available. Move the handling for this to the relevant subdevs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn/cmdq: move command generation to subdevsBen Skeggs
This moves the code to generate commands for the ACR unit of the PMU/SEC2 LS firmwares to those subdevs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn/cmdq: split the condition for queue readiness vs pmu acr ↵Ben Skeggs
readiness This is to allow for proper separation of the LS interface code from the queue handling code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn/qmgr: move sequence tracking from nvkm_msgqueue to ↵Ben Skeggs
nvkm_falcon_qmgr Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn: split msgqueue into multiple piecesBen Skeggs
To make things clearer while modifying the interfaces, split msgqueue into Queue Manager, Command Queue, and Message Queue. There should be no code changes here, these will be done incrementally. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn: specify queue register offsets from subdevBen Skeggs
Also fixes the values for Turing, even though we don't use it yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/falcon: fix a few indentation issuesColin Ian King
There are a few statements that are indented incorrectly. Fix these. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gv100: initial supportBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-02-02drm/nouveau/secboot/gp108: implement on top of acr_r370Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Gourav Samaiya <gsamaiya@nvidia.com>
2017-08-22drm/nouveau/falcon: use a more reasonable msgqueue timeout valueBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/msgqueue: support for GP10B PMU firmwareAlexandre Courbot
The GP10B firmware is very close to GM20B's. The only difference is that it supports booting multiple falcons. In order to avoid having too much functions and structures shared, implement its support in the same source file as GM20B firmware. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/secboot: pass instance to LS firmware loadersAlexandre Courbot
Having access to the secboot instance loading a LS firmware can be useful to LS firmware handlers. At least more useful than just having an out-of-context subdev pointer. GP10B's firmware will also need to know the WPR address, which can be obtained from the secboot instance. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/secboot: allow to boot multiple falconsAlexandre Courbot
Change the secboot and msgqueue interfaces to take a mask of falcons to reset instead of a single falcon. The GP10B firmware interface requires FECS and GPCCS to be booted in a single firmware command. For firmwares that only support single falcon boot, it is trivial to loop over the mask and boot each falcons individually. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-17drm/nouveau/secboot: fix NULL pointer dereferenceAlexandre Courbot
The msgqueue pointer validity should be checked by its owner, not by the msgqueue code itself to avoid this situation. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reported-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-07drm/nouveau/falcon: support for gp10x msgqueueAlexandre Courbot
Add support for the msgqueue firmware used to process SEC2 commands for gp10x chips. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07drm/nouveau/falcon/msgqueue: add SEC2 supportAlexandre Courbot
Add support for running a msgqueue on the SEC2 falcon. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07drm/nouveau/falcon: support for gm20b msgqueueAlexandre Courbot
Add support for the msgqueue firmware used to process PMU commands for gm20b. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07drm/nouveau/falcon: add msgqueue interfaceAlexandre Courbot
A message queue firmware implements a specific protocol allowing the host to send "commands" to a falcon, and the falcon to reply using "messages". This patch implements the common part of this protocol and defines the interface that the host can use. Due to the way the firmware is developped internally at NVIDIA (where kernel driver and firmware evolve in lockstep), firmwares taken at different points in time can have frustratingly subtle differences that must be taken into account. This code is architectured to make implementing such differences as easy as possible. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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