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path: root/drivers/gpu/drm/i915/i915_reg.h
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2025-02-17drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTLImre Deak
Fix the port width programming in the DDI_BUF_CTL register on MTLP+, where this had an off-by-one error. Cc: <stable@vger.kernel.org> # v6.5+ Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI") Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-3-imre.deak@intel.com (cherry picked from commit b2ecdabe46d23db275f94cd7c46ca414a144818b) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-12-16drm/i915: move DDI_CLK_VALFREQ next to other Cx0 PHY registersJani Nikula
Relocate DDI_CLK_VALFREQ register definition next to other Cx0 PHY register macros. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213115111.335474-3-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-16drm/i915: relocate _VGA_MSR_WRITE register definitionJani Nikula
Move _VGA_MSR_WRITE to intel_crt_regs.h. It's not necessarily the optimal place for it, but hands down better than i915_reg.h. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213115111.335474-2-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-16drm/i915: split out i9xx_wm_regs.hJani Nikula
Very few files need the i9xx watermark related registers. Split them out to a dedicated file. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213115111.335474-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-11drm/i915/dg2: Implement Wa_14022698537Raag Jadav
G8 power state entry is disabled due to a limitation on DG2, so we enable it from driver with Wa_14022698537. For now we enable it for all DG2 devices with the exception of a few, for which, we enable only when paired with whitelisted CPU models. This works with native ASPM and reduces idle power consumption. $ echo powersave > /sys/module/pcie_aspm/parameters/policy $ lspci -s 0000:03:00.0 -vvv LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk- v2: Fix Wa_ID and include it in subject (Badal) Rephrase commit message (Jani) v3: Move workaround to i915_pcode_init() (Badal, Anshuman) Re-order macro (Riana) v4: Spell fix (Riana) Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241211115952.1659287-5-raag.jadav@intel.com
2024-11-22drm/i915/reg: convert DP_TP_CTL/DP_TP_STATUS to REG_BIT() and friendsJani Nikula
Use the modern style for defining register contents. Expand the status register contents a bit. TODO: There are more VC payload mapping fields, spanning more registers, and have more bits on more recent platforms. v2: - Fix DP_TP_STATUS_STREAMS_ENABLED_MASK mask (Imre) - Drop status VC3 payload mapping for now Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1ef15e6bb58ca847f89c9b39cbc9771cb57db408.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-12drm/i915/display: make CHICKEN_TRANS() display version awareJani Nikula
Making register macros platform or display version aware is not exactly something I want to promote widely, but in this case it's the lesser of two evils. hsw_chicken_trans_reg() is not pretty, and it doesn't have a suitable home. v2: Rebase Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/712c17ee22537b0628aa32695743bc017b3fe332.1731409802.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-11drm/i915/crt: Extract intel_crt_regs.hVille Syrjälä
Move the analog port register definitions into their own file. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241107161123.16269-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-11-11drm/i915/crt: Clean up ADPA_HOTPLUG_BITS definitionsVille Syrjälä
ADPA_HOTPLUG_BITS is defined in terms of the individual register bits and is defined in intel_crt.c, whereas the counterpart mask (ADPA_CRT_HOTPLUG_MASK) is just defined as a raw hex constant and lives in i915_reg.h. Just define both the same way (with unified name to boot) and move both to intel_crt.c since they are more an implementation detail rather than anything to do with the actual register definitions. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241107161123.16269-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-11-11drm/i915/crt: Use REG_BIT() & co.Ville Syrjälä
Follow the modern style and use REG_BIT() & co. for the analog port register definitions. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241107161123.16269-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-11-11drm/i915/crt: Drop the unused ADPA_DPMS bit definitionsVille Syrjälä
The ADPA_DPMS bit definitions are just an alias for the sync disable bits, and unused one at that. Drop the pointless definitions. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241107161123.16269-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-11-11drm/i915/psr: add LATENCY_REPORTING_REMOVED() register bit helperJani Nikula
Drop the wa_16013835468_bit_get() function in favour of the register macro. It doesn't have to be so complicated, and we don't have to use the workaround name in everything that's related to it. Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/22934fee1ea37c777c35e4b520d5f11b6cd953d0.1730201504.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-05drm/i915/xe3lpd: Update HDCP rekeying bitSuraj Kandpal
The TRANS_DDI_FUNC_CTL bit used to enable/disable HDCP rekeying has moved from bit 12 (Xe2) to bit 15 (Xe3); update the RMW toggle accordingly. Also drop the misleading workaround comment tag on this function since disabling of HDCP rekeying is something that happens on all platforms, not just those impacted by that workaround. While we're here, also re-order the if/else ladder to use standard "newest platform first" order. v2: add additional definition instead of function, commit message typo fix and update. v3: restore lost conditional from v2. v4: subject line and subject message updated, fix the if ladder order, fix the bit definition order. v5: Add the bspec link and remove the Wa comment tag v6: Rebase over new changes v7: Fix commit subject and message, reladder the if/else blocks Bspec: 69964 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241104185055.739605-1-suraj.kandpal@intel.com
2024-10-31drm/i915: Implement Dbuf overlap detection feature starting from LNLStanislav Lisovskiy
From LNL onwards there is a new hardware feature, which allows to detect if the driver wrongly allocated DBuf entries and they happen to overlap. If enabled this will cause a specific interrupt to occur. We now handle it in the driver, by writing correspondent error message to kernel log. v2: Initialize dbuf overlap flag in runtime_defaults (Jani Nikula) v3: Unmask the overlap detection interrupt (Uma) v4: use display over i915 (Jani Nikula) v5: Use display instead of dev_priv (Jani Nikula) v6: rebased to resolve merge conflicts Bspec: 69450, 69464 Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241030103319.207235-1-vinod.govindapillai@intel.com
2024-10-29drm/i915/xe3lpd: Update pmdemand programmingMatt Roper
There are some minor changes to pmdemand handling on Xe3: - Active scalers are no longer tracked. We can simply skip the readout and programming of this field. - Active dbuf slices are no longer tracked. We should skip the readout and programming of this field and also make sure that it stays 0 in our software bookkeeping so that we won't erroneously return true from intel_pmdemand_needs_update() due to mismatches. - Even though there aren't enough pipes to utilize them, the size of the 'active pipes' field has expanded to four bits, taking over the register bits previously used for dbuf slices. Since the lower bits of the mask have moved, we need to update our reads/writes to handle this properly. v2: active pipes is no longer always max 3, add in the ability to go to 4 for PTL. v3: use intel_display for display_ver check, use INTEL_NUM_PIPES v4: add a conditional for number of pipes macro vs using 3. v5: reverse conditional order of v4. v6: undo v5 and fix num_pipes assignment v7: pass display struct instead of i915, checkpatch fix v8: Alignment issue Bspec: 68883, 69125 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241028193015.3241858-2-clinton.a.taylor@intel.com
2024-10-17drm/i915: Remove unused underrun irq/reporting bitsSai Teja Pottumuttu
Underrun recovery was defeatured and was never brought into usage. Thus we can remove the underrun recovery interrupt/reporting register bits and related logic introduced to detect/report soft, hard, port underruns. Essentially this is a revert of the commit 8bcc0840cf7c ("drm/i915/xelpd: Enhanced pipe underrun reporting") which originally added this functionality. Also note that PIPE_STATUS_UNDERRUN bit in PIPESTATUS still stays relevant but we would move back to not clearing this sticky bit as we are not using any information from this register. v2: Extend commit message to add more details (Matt Roper) v3: Fix the old commit mention in commit message Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241015080503.3521063-1-sai.teja.pottumuttu@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-10-03drm/i915/irq: remove GEN8_IRQ_RESET_NDX() and GEN8_IRQ_INIT_NDX() macrosJani Nikula
Define register offset triplets for all registers used with GEN8_IRQ_RESET_NDX() and GEN8_IRQ_INIT_NDX() macros, and call the underlying gen3_irq_reset() and gen3_irq_init() functions directly. Remove the macros, along with the macro name concatenation hackery. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241002102645.136155-3-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-10-03drm/i915/irq: remove GEN3_IRQ_RESET() and GEN3_IRQ_INIT() macrosJani Nikula
Define register offset triplets for all registers used with GEN3_IRQ_RESET() and GEN3_IRQ_INIT() macros, and call the underlying gen3_irq_reset() and gen3_irq_init() functions directly. Remove the macros, along with the macro name concatenation hackery. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241002102645.136155-2-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: remove superfluous whitespaceJani Nikula
Clean up some whitespace. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1223c6c7ff59f541453a38f8f5e2df9eb3526573.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: remove unused DSI register macrosJani Nikula
Not needed. Remove. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2a8633038c0bd6ca06236558a609e021b30514f4.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: fix small register style issues here and thereJani Nikula
Adhere to the style described at the top of i915_reg.h. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0bbb79008bb83bc56669a1e969978769539d6c62.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: fix DIP CTL register styleJani Nikula
Adhere to the style described at the top of i915_reg.h. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/fdc607b716cf86b8bc88c15a43bc7088c5aab05f.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: fix PCH transcoder timing and data/link m/n styleJani Nikula
Adhere to the style described at the top of i915_reg.h. v2: Rebase with the indentation fixed (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1 Link: https://patchwork.freedesktop.org/patch/msgid/90b1145453050797d3030bc2e5e24da18f34bdda.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: fix PCH transcoder timing indentationJani Nikula
Adhere to the style described at the top of i915_reg.h. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f56e48a927692cec382e292602e0fa68e37f3b93.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: fix SKL scaler register styleJani Nikula
Adhere to the style described at the top of i915_reg.h. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0c6188d7afe688b43734ee4ef5f2c403f805bd48.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: fix pipe data/link m/n register styleJani Nikula
Adhere to the style described at the top of i915_reg.h. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/99fb1c8aabb7646ca2565db0b969cf15d9103318.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: fix pipe conf, stat etc. register styleJani Nikula
Adhere to the style described at the top of i915_reg.h. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4360912222c8c0516d84253c3a05ef1cf421da01.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: fix g4x pipe data/link m/n register styleJani Nikula
Adhere to the style described at the top of i915_reg.h. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f55960ce8cdcf654e5de19274c7b67b3d3497550.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-11drm/i915/reg: fix transcoder timing register styleJani Nikula
Adhere to the style described at the top of i915_reg.h. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/fcd7c5114f707da8018c65fbb44a70dbdceec37f.1725974820.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-08-29drm/i915/dsb: Hook up DSB error interruptsVille Syrjälä
Enable all DSB error/fault interrupts so that we can see if anything goes terribly wrong. v2: Pass intel_display to DISPLAY_VER() (Jani) Drop extra '/' from drm_err() for consistency v3: Reorder the irq handler a bit Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240625135852.13431-1-ville.syrjala@linux.intel.com Reviewed-by: Animesh Manna <animesh.manna@intel.com>
2024-08-12drm/i915/bmg: Read display register timeoutMitul Golani
Log the address of the register that caused the timeout interrupt by reading RMTIMEOUTREG_CAPTURE --v2: - Update RMTIMEOUTREG_CAPTURE naming (Suraj) --v3: - XeLpdp naming convention. - Use if condition instead of else if Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240807142106.1270213-1-mitulkumar.ajitkumar.golani@intel.com
2024-06-19drm/i915: Enable plane/pipeDMC ATS fault interrupts on mtlVille Syrjälä
MTL has some new IOMMU thing that has a few new fault interrupts. Enable those so we can know if things are going poorly. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-19drm/i915: Enable pipeDMC fault interrupts on tgl+Ville Syrjälä
PipeDMC has its own fault interrupt. Enable that so that we can know if things are failing. While at it, define the other pipeDMC interrupt as well, even though we're not currently using it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-19drm/i915: Nuke the intermediate pipe fault bitmasksVille Syrjälä
GEN8_DE_PIPE_IRQ_FAULT_ERRORS & co. don't really achieve anything. Get rid of them and just declare all the bits directly in gen8_de_pipe_fault_mask(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-19drm/i915: Extend GEN9_PIPE_PLANE_FLIP_DONE() to cover all universal planesVille Syrjälä
GEN9_PIPE_PLANE_FLIP_DONE() only works for planes 1-4. Extend it handle planes 5-7 as well. Somewhat annoyingly the bits are spread around into two distinct clumps. Currently this doesn't achieve anything, but if we ever extend async flip support to more than just the first plane then we'll need this. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-19drm/i915: Sort bdw+ pipe interrupt bitsVille Syrjälä
It's really hard to figure out which bdw+ pipe interrupt bits we've defined and which we have not. Sort the defines to make that a bit easier (still not super easy since the bits have been shuffled a bit over the years). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-19drm/i915: Document bdw+ pipe interrupt bitsVille Syrjälä
Sprinkle some notes indicating which platforms have which pipe interrupt bits. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-19drm/i915: Use REG_BIT() for bdw+ pipe interruptsVille Syrjälä
Replace the hand rolled (1<<n) with the modern REG_BIT() approach for the bdw+ pipe interrupt bits. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-14drm/i915: remove unused pipe/plane B register macrosJani Nikula
None of these are used. The parametrized register macros all depend on the pipe/plane A offset macros alone. Remove the unused ones. v2: Rebase Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/16d278bea466a69cdce94fd83d98dd15ce1a8c89.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-14drm/i915: relocate some DSPCNTR reg bit definitionsJani Nikula
Some plane B/C specific bits were left next to the unused _DSPBCNTR macro. Move them next to the DSPCNTR() macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/85409fbe5073797c0dc17df43eeb25abe9ff889f.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-11drm/i915: Separate VRR related register definitionsMitul Golani
Move VRR related register definitions to a separate file called intel_vrr_regs.h. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-3-mitulkumar.ajitkumar.golani@intel.com
2024-06-11drm/i915: Update indentation for VRR registers and bitsMitul Golani
Update the indentation for the VRR register definition and its bits, and fix checkpatch issues to ensure smooth movement of registers and bits. --v2: - Keep XELPD_VRR_CTL_VRR_GUARDBAND(x) to avoid readability (Ankit). - Fix all indentation related VRR registers and bits instead of checkpatch one. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-2-mitulkumar.ajitkumar.golani@intel.com
2024-06-07drm/i915: pass dev_priv explicitly to HSW_STEREO_3D_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the HSW_STEREO_3D_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/76f980f5ed3638746c6b58dec7d0bd8c43a37987.1717514638.git.jani.nikula@intel.com
2024-06-07drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANSJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the MTL_CLKGATE_DIS_TRANS register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b330d86c5e3012513daa36dceffd2db45f0d7850.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCYJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_SET_CONTEXT_LATENCY register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/989f89994edae0829e3b6d5d6e3d8a521f0eda00.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_MSA_MISCJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_MSA_MISC register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1a9c0a0f8c5bba31138f0c7aebdf839b9b30298c.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUSJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TGL_DP_TP_STATUS register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c7aaf0e981324bfc5b3aec31f30a7b1a158ba568.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TGL_DP_TP_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3d3e2b732ec9372cf6b1ae44b25342179b028b1a.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2Jani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_DDI_FUNC_CTL2 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2b61bf9c1f74ae633c99aa34fbf1aa85735cc5b6.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_DDI_FUNC_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4ccf75561aa0fb209fd71c85e9089b0350570fd6.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-05 09:48:16 +0000