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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2025-02-17drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTLImre Deak
2024-12-16drm/i915: move DDI_CLK_VALFREQ next to other Cx0 PHY registersJani Nikula
2024-12-16drm/i915: relocate _VGA_MSR_WRITE register definitionJani Nikula
2024-12-16drm/i915: split out i9xx_wm_regs.hJani Nikula
2024-12-11drm/i915/dg2: Implement Wa_14022698537Raag Jadav
2024-11-22drm/i915/reg: convert DP_TP_CTL/DP_TP_STATUS to REG_BIT() and friendsJani Nikula
2024-11-12drm/i915/display: make CHICKEN_TRANS() display version awareJani Nikula
2024-11-11drm/i915/crt: Extract intel_crt_regs.hVille Syrjälä
2024-11-11drm/i915/crt: Clean up ADPA_HOTPLUG_BITS definitionsVille Syrjälä
2024-11-11drm/i915/crt: Use REG_BIT() & co.Ville Syrjälä
2024-11-11drm/i915/crt: Drop the unused ADPA_DPMS bit definitionsVille Syrjälä
2024-11-11drm/i915/psr: add LATENCY_REPORTING_REMOVED() register bit helperJani Nikula
2024-11-05drm/i915/xe3lpd: Update HDCP rekeying bitSuraj Kandpal
2024-10-31drm/i915: Implement Dbuf overlap detection feature starting from LNLStanislav Lisovskiy
2024-10-29drm/i915/xe3lpd: Update pmdemand programmingMatt Roper
2024-10-17drm/i915: Remove unused underrun irq/reporting bitsSai Teja Pottumuttu
2024-10-03drm/i915/irq: remove GEN8_IRQ_RESET_NDX() and GEN8_IRQ_INIT_NDX() macrosJani Nikula
2024-10-03drm/i915/irq: remove GEN3_IRQ_RESET() and GEN3_IRQ_INIT() macrosJani Nikula
2024-09-11drm/i915/reg: remove superfluous whitespaceJani Nikula
2024-09-11drm/i915/reg: remove unused DSI register macrosJani Nikula
2024-09-11drm/i915/reg: fix small register style issues here and thereJani Nikula
2024-09-11drm/i915/reg: fix DIP CTL register styleJani Nikula
2024-09-11drm/i915/reg: fix PCH transcoder timing and data/link m/n styleJani Nikula
2024-09-11drm/i915/reg: fix PCH transcoder timing indentationJani Nikula
2024-09-11drm/i915/reg: fix SKL scaler register styleJani Nikula
2024-09-11drm/i915/reg: fix pipe data/link m/n register styleJani Nikula
2024-09-11drm/i915/reg: fix pipe conf, stat etc. register styleJani Nikula
2024-09-11drm/i915/reg: fix g4x pipe data/link m/n register styleJani Nikula
2024-09-11drm/i915/reg: fix transcoder timing register styleJani Nikula
2024-08-29drm/i915/dsb: Hook up DSB error interruptsVille Syrjälä
2024-08-12drm/i915/bmg: Read display register timeoutMitul Golani
2024-06-19drm/i915: Enable plane/pipeDMC ATS fault interrupts on mtlVille Syrjälä
2024-06-19drm/i915: Enable pipeDMC fault interrupts on tgl+Ville Syrjälä
2024-06-19drm/i915: Nuke the intermediate pipe fault bitmasksVille Syrjälä
2024-06-19drm/i915: Extend GEN9_PIPE_PLANE_FLIP_DONE() to cover all universal planesVille Syrjälä
2024-06-19drm/i915: Sort bdw+ pipe interrupt bitsVille Syrjälä
2024-06-19drm/i915: Document bdw+ pipe interrupt bitsVille Syrjälä
2024-06-19drm/i915: Use REG_BIT() for bdw+ pipe interruptsVille Syrjälä
2024-06-14drm/i915: remove unused pipe/plane B register macrosJani Nikula
2024-06-14drm/i915: relocate some DSPCNTR reg bit definitionsJani Nikula
2024-06-11drm/i915: Separate VRR related register definitionsMitul Golani
2024-06-11drm/i915: Update indentation for VRR registers and bitsMitul Golani
2024-06-07drm/i915: pass dev_priv explicitly to HSW_STEREO_3D_CTLJani Nikula
2024-06-07drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANSJani Nikula
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCYJani Nikula
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_MSA_MISCJani Nikula
2024-06-07drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUSJani Nikula
2024-06-07drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTLJani Nikula
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2Jani Nikula
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTLJani Nikula
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-03 08:49:52 +0000