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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
AgeCommit message (Expand)Author
2023-08-07drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics stepDnyaneshwar Bhadane
2023-08-07drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform definesDnyaneshwar Bhadane
2023-08-07drm/i915/hsw: s/HSW/HASWELL for platform/subplatform definesDnyaneshwar Bhadane
2023-05-16drm/i915: Make the CRTC state consistent during sanitize-disablingImre Deak
2023-05-16drm/i915: Add helpers to reference/unreference a DPLL for a CRTCImre Deak
2023-05-15drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula
2023-05-15drm/i915/dpll: drop a useless I915_STATE_WARN_ON()Jani Nikula
2023-04-14drm/i915/mtl: Add Support for C10 PHY message bus and pll programmingRadhakrishna Sripada
2023-02-16drm/i915/display/dpll: use intel_de_rmw if possibleAndrzej Hajda
2023-01-18drm/i915: move pch_ssc_use to display sub-struct under dpllJani Nikula
2022-11-17drm/i915/hti: abstract hti handlingJani Nikula
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula
2022-10-26drm/i915/tgl+: Sanitize DKL PHY register definitionsImre Deak
2022-10-26drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.hImre Deak
2022-10-26drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.hImre Deak
2022-10-26drm/i915/tgl+: Add locking around DKL PHY register accessesImre Deak
2022-09-26drm/i915: Nuke intel_get_shared_dpll_id()Ville Syrjälä
2022-09-26drm/i915: Always initialize dpll.lockVille Syrjälä
2022-09-26drm/i915: WARN if PLL ref/unref got messed upVille Syrjälä
2022-09-26drm/i915: Pimp DPLL ref/unref debugsVille Syrjälä
2022-09-26drm/i915: Drop pointless 'budget' variableVille Syrjälä
2022-09-08drm/i915: Set active dpll early for icl+Ville Syrjälä
2022-09-08drm/i915: Feed the DPLL output freq back into crtc_stateVille Syrjälä
2022-09-07drm/i915: Shuffle some PLL code aroundVille Syrjälä
2022-08-31drm/i915/dpll: replace BUG_ON() with drm_WARN_ON()Jani Nikula
2022-08-31drm/i915: move vbt to display.vbtJani Nikula
2022-08-31drm/i915: move and group cdclk under display.cdclkJani Nikula
2022-08-29drm/i915: move dpll under display.dpllJani Nikula
2022-06-28drm/i915: Fix error code in icl_compute_combo_phy_dpll()Dan Carpenter
2022-06-17drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.cJani Nikula
2022-06-16drm/i915: Implement w/a 22010492432 for adl-sVille Syrjälä
2022-05-31drm/i915: Clean up DPLL related debugsVille Syrjälä
2022-05-31drm/i915: Split shared dpll .get_dplls() into compute and get phasesVille Syrjälä
2022-04-25drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()Ville Syrjälä
2022-04-25drm/i915: Pass dev_priv to intel_shared_dpll_init()Ville Syrjälä
2022-04-25drm/i915: Make .get_dplls() return intVille Syrjälä
2022-03-10drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()Ville Syrjälä
2022-03-10drm/i915: Replace bxt_clk_div with struct dpllVille Syrjälä
2022-03-10drm/i915: Store the m2 divider as a whole in bxt_clk_divVille Syrjälä
2022-03-10drm/i915: Clean up bxt/glk PLL registersVille Syrjälä
2022-03-04drm/i915: Use designated initializers for bxt_dp_clk_val[]Ville Syrjälä
2022-03-04drm/i915: Remove bxt m2_frac_enVille Syrjälä
2022-03-04drm/i915: Clean up some struct/array initializersVille Syrjälä
2022-03-04drm/i915: Move a bunch of stuff into rodata from the stackVille Syrjälä
2022-03-04drm/i915: Nuke skl_wrpll_context_init()Ville Syrjälä
2022-03-02drm/i915: Use str_on_off()Lucas De Marchi
2022-02-18drm/i915/display/tgl+: Implement new PLL programming stepJosé Roberto de Souza
2022-01-19drm/i915/dpll: make intel_shared_dpll_funcs internal to intel_dpll_mgr.cJani Nikula
2022-01-11drm/i915: Move TC PHY registers to their own headerMatt Roper
2021-10-20drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFFJosé Roberto de Souza
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