summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
AgeCommit message (Expand)Author
2020-11-16drm: fix some kernel-doc markupsMauro Carvalho Chehab
2020-10-15drm/i915/dg1: Enable DPLL for DG1Lucas De Marchi
2020-10-15drm/i915/dg1: Add and setup DPLLs for DG1Aditya Swarup
2020-10-14drm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay
2020-10-06drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clockImre Deak
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak
2020-09-15drm/i915/pll: Centralize PLL_ENABLE register lookupAnusha Srivatsa
2020-09-08Merge tag 'v5.9-rc4' into drm-nextDave Airlie
2020-08-23treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva
2020-08-17drm/i915/rkl: Handle HTIMatt Roper
2020-08-17drm/i915/rkl: Add DPLL4 supportMatt Roper
2020-07-01drm/i915/icl+: Simplify combo/TBT PLL calculation call-chainImre Deak
2020-07-01drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clockImre Deak
2020-04-21drm/i915/display/dpll_mgr: Prefer drm_WARN_ON over WARN_ONPankaj Bharadiya
2020-03-09drm/i915: Fix documentation for intel_dpll_get_freq()Imre Deak
2020-03-02drm/i915: Unify the DPLL ref clock frequency trackingImre Deak
2020-03-02drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out againImre Deak
2020-03-02drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculationImre Deak
2020-03-02drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculationImre Deak
2020-03-02drm/i915/hsw: Split out the SPLL parameter calculationImre Deak
2020-03-02drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLLImre Deak
2020-03-02drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding itImre Deak
2020-03-02drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.cImre Deak
2020-03-02drm/i915: Move the DPLL vfunc inits after the func definesImre Deak
2020-03-02drm/i915: Keep the global DPLL state in a DPLL specific structImre Deak
2020-03-02drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.cImre Deak
2020-03-02drm/i915: Fix bounds check in intel_get_shared_dpll_id()Imre Deak
2020-02-11drm/i915/dpll_mgr: convert to drm_device based logging macros.Wambui Karuga
2020-02-04drm/i915/display/dpll_mgr: Make WARN* drm specific where drm_device ptr is av...Pankaj Bharadiya
2020-01-27drm/i915/dpll_mgr: use intel_de_*() functions for register accessJani Nikula
2020-01-13drm/i915: Pass intel_encoder to enc_to_*()Ville Syrjälä
2019-11-01drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.Maarten Lankhorst
2019-10-25drm/i915: Fix PCH reference clock for FDI on HSW/BDWVille Syrjälä
2019-10-09drm/i915: Select DPLL's via maskMatt Roper
2019-10-04drm/i915/tgl: Add the Thunderbolt PLL divider valuesImre Deak
2019-09-27drm/i915/tgl: Fix dkl link trainingJosé Roberto de Souza
2019-09-25drm/i915/tgl: Add dkl phy pll calculationsJosé Roberto de Souza
2019-09-25drm/i915/tgl: re-indent code to prepare for DKL changesLucas De Marchi
2019-09-25drm/i915/tgl: Add support for dkl pll writeVandita Kulkarni
2019-09-25drm/i915/tgl: Add initial dkl pll supportLucas De Marchi
2019-09-23drm/i915/tgl/pll: Set update_active_dpllClinton A Taylor
2019-09-02drm/i915: Prefer encoder->name over port_name()Ville Syrjälä
2019-08-16drm/i915: Wrappers for display register waitsDaniele Ceraolo Spurio
2019-08-07drm/i915: rename intel_drv.h to display/intel_display_types.hJani Nikula
2019-07-18drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1Vivek Kasireddy
2019-07-11drm/i915/tgl: Update DPLL clock reference registerJosé Roberto de Souza
2019-07-11drm/i915/tgl: Add DPLL registersLucas De Marchi
2019-07-11drm/i915/tgl: Add pll managerVandita Kulkarni
2019-07-11drm/i915: Polish intel_shared_dpll_swap_state()Ville Syrjälä
2019-07-10drm/i915: Transition port type checks to phy checksMatt Roper
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-28 13:24:11 +0000