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path: root/drivers/gpu/drm/i915/display/intel_cx0_phy.c
AgeCommit message (Expand)Author
2023-06-26drm/i915/mtl: Fix SSC selection for MPLLARadhakrishna Sripada
2023-06-05drm/i915/mtl: Reset only one lane in case of MFDMika Kahola
2023-05-19drm/i915/hdmi: C20 computed PLL frequenciesClint Taylor
2023-05-18drm/i915/mtl: Fix expected reg value for Thunderbolt PLL disablingMika Kahola
2023-05-15drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula
2023-04-28drm/i915/mtl: Power up TCSSMika Kahola
2023-04-28drm/i915/mtl: Readout Thunderbolt HW stateMika Kahola
2023-04-28drm/i915/mtl: Enabling/disabling sequence Thunderbolt pllMika Kahola
2023-04-28drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLAMika Kahola
2023-04-28drm/i915/mtl: C20 port clock calculationMika Kahola
2023-04-28drm/i915/mtl: Dump C20 pll hw stateMika Kahola
2023-04-28drm/i915/mtl: C20 HW readoutMika Kahola
2023-04-28drm/i915/mtl: C20 PLL programmingMika Kahola
2023-04-15drm/i915: Make intel_{mpllb,c10pll}_state_verify() saferVille Syrjälä
2023-04-14drm/i915/mtl: Add C10 phy programming for HDMIRadhakrishna Sripada
2023-04-14drm/i915/mtl: Add vswing programming for C10 physMika Kahola
2023-04-14drm/i915/mtl: Add Support for C10 PHY message bus and pll programmingRadhakrishna Sripada