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path: root/drivers/gpu/drm/amd/display/dc/inc
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2020-11-04drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher
Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2Joshua Aberback
[Why] Prior commit "Blank HUBP during pixel data blank for DCN30" missed the call to set_disp_pattern_generator from set_crtc_test_pattern, which re-exposed the issue for which we initially blocked active-only p-state switching. [How] - remove dcn30_blank_pixel_data, set dcn30 back to dcn20 version - new hwss funciton set_disp_pattern_generator - dcn20 version just calls opp_set_disp_pattern_generator - dcn30 version implements the HUBP blank Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: correct eDP T9 delayHugo Hu
[Why] The current end of T9 delay is relay on polling sink status by DPCD. But the polling for sink status change after NoVideoStream_flag set to 0. [How] Add function edp_add_delay_for_T9 to add T9 delay. Move the sink status polling after blank. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: fail instead of div by zero/bugcheckAshley Thomas
[why] If pbn_per_slot is 0, fail instead of dividing by zero and bugchecking. [how] Check for zero divisor before division operation. Signed-off-by: Ashley Thomas <Ashley.Thomas2@amd.com> Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-26drm/amd/display: Update GSL state if leaving immediate flipAlvin Lee
[Why] We should leave GSL if we're not doing immediate flip no matter if we're doing pipe split or not [How] Check for updating GSL state whenever we're not doing immediate flip v2: Squash in build fix (Alex) Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-26drm/amd/display: Revert check for flip pending before locking pipesIsabel Zhang
[Why] Causes underflow regression [How] This reverts commit 99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1 Signed-off-by: Isabel Zhang <isabel.zhang@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-26drm/amd/display: Define PSR ERROR Status bit VSC_SDPReza Amini
[why] So we can track VSC SDP errors from display [how] Define the bit, and use it in driver logic Signed-off-by: Reza Amini <Reza.Amini@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-26drm/amd/display: Raise DPG height during timing synchronizationTaimur Hassan
[Why] Underflow counter increases in AGM when performing some mode switches due to timing sync, which is a known hardware issue. [How] Temporarily raise DPG height during timing sync so that underflow is not reported. Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-26drm/amd/display: Source minimum HBlank supportAshley Thomas
[Why] Some sink devices wish to have access to the minimum HBlank supported by the ASIC. [How] Make the ASIC minimum HBlank available in Source Device information address 0x340. Signed-off-by: Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amd/display: Block ABM in case of eDP ODMYongqiang Sun
[Why] enable ODM on eDP panel with ABM will result in color difference on the panel due to only one ABM module to set one pipe. [How] Block ABM in case of ODM enabled on eDP. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amd/display: Copy WM values from set A to other sets in hw_initJoshua Aberback
[Why] When we transfer the WM range table to SMU, they can perform a watermark switch right away. This can be a problem if we're in not in accelerated mode during hw_init as SMU may initiate a dummy p-state change before the rest of the watermarks are programmed. Watermark set A is defined to be sufficient for all cases, so we can copy the values from set A to all other sets, avoiding any issues from SMU doing WM switches. [How] - new hubbub func init_watermarks - copy register values from set A to all other sets - call init_watermarks before calling notify_wm_ranges Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amd/display: Force enable pstate on driver unloadJoshua Aberback
[Why] During driver unload, it is expected that p-state switching is supported. If it's not supported, PMFW will hang due to a forced p-state switch. Even if the current timing does not support p-state normally, we still want to force allow because the worst that can happen is underflow. This will match Navi10 behaviour. [How] - new hubbub func to control the force pstate register - force allow when releasing display ownership - registers are inaccessible after due to m_cgs.hwNotAvailable - explicitly disable force signal during hw_init - if driver is disabled and re-enabled, register not cleared otherwise Also, remove DCN3 part of dcn10_init_hw, we will not be going back to it. Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amd/display: Check for flip pending before locking pipesAric Cyr
[Why] When running games or benchmarking with v-sync disabled, disabling a plane (which is v-sync) can cause underflow. This is caused by flips pending before pipe locking being applied after locks are released and pipes could have been re-arranged or disconnected. This could potentially apply a flip on incorrect pipe. Also, previous logic of always locking pipes was unnecessary. [How] Only lock the pipes when there is a pipe being disabled to increase efficiency. Before the pipes are locked, check that any pending flips are cleared to ensure the flips are applied to the correct pipe. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amd/display: Add dcn3.01 support to DC (v2)Roman Li
Update dc for vangogh support. v2: fix compilation without DCN 301 set. Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: Revert check for flip pending before locking pipesAric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-29drm/amd/display: Calc DLG from dummy p-state if full p-state unsupportedJoshua Aberback
[Why] Currently, when full p-state changes are not supported, DLG parameters are calculated for no p-state support at all. However, we are required to always support dummy p-state changes, so we should instead calculate DLG based on dummy p-state latency when full p-state is unsupported. This behaviour already exists for DCN2. [How] - move DLG calculation inside WM calculation - if p-state unsupported, do not recalculate for set A, instead copy from set C, and perform DLG calculation with dummy p-state latency Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amd/display: Check for flip pending before locking pipes.Taimur Hassan
[Why] When running a game/benchmark with v-sync disabled, disabling a plane (which is v-sync) can cause an underflow. This is due to flips that are pending before pipe locking being applied after locks are released and pipes have been re-arranged or disconnected. This can potentially apply a flip on the incorrect pipe. [How] Check that any pending flips are cleared before locking any pipes to ensure flips are applied on the correct pipes. Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: implement notify stream maskEric Yang
[Why] Send stream active state info to DMUB [How] Implement GPINT to notify stream mask Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: adding pathway to retrieve stutter periodMartin Leung
why: some functions may need be dependent on stutter period in the future how: Extract from stutter calculations and place into perf_params structure Signed-off-by: Martin Leung <martin.leung@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: Rename set_mst_bandwidth to align with DP specGeorge Shen
[Why] The function set_mst_bandwidth is poorly name since it isn't clear what it does, and it also does not reflect any part of the allocation sequence described in the DP spec. [How] Rename the function set_mst_bandwidth to set_throttled_vcp_size. Signed-off-by: George Shen <george.shen@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/display: Detect plane change when detect pipe change.JinZe.Xu
[Why] If plane has changed, dcn20_detect_pipe_changes doesn't update dc_plane_state->update_flags, and the following dcn20_program_pipe can't reprogram hubp correctly. [How] Add a new flags bit "plane_changed" in pipe_ctx->update_flags.If old plane isn’t identical to new plane, this bit will be set and guide “dcn20_program_pipe” to programing HUBP correctly. Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-26drm/amd/display: Send DISPLAY_OFF after power down on bootSung Lee
[WHY] update_clocks might not be called on headless adapters. This means DISPLAY_OFF may not be sent in headless cases. [HOW] If hardware is powered down on boot because it is headless (mode set does not happen on that adapter) also send DISPLAY_OFF notification. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-17drm/amd/display: Add read backlight interfaceYongqiang Sun
[Why & How] Add read backlight interface to get ABM data. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-10drm/amd/display: Disconnect pipe separetely when disable pipe splitAlvin Lee
[Why] When changing pixel formats for HDR (e.g. ARGB -> FP16) there are configurations that change from 2 pipes to 1 pipe. In these cases, it seems that disconnecting MPCC and doing a surface update at the same time(after unlocking) causes some registers to be updated slightly faster than others after unlocking (e.g. if the pixel format is updated to FP16 before the new surface address is programmed, we get corruption on the screen because the pixel formats aren't matching). We separate disconnecting MPCC from the rest of the pipe programming sequence to prevent this. [How] Move MPCC disconnect into separate operation than the rest of the pipe programming. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-10drm/amd/display: Revert regressionAlvin Lee
[Why] Caused pipe split regression Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-04drm/amd/display: Separate pipe disconnect from rest of progrmamingAlvin Lee
[Why] When changing pixel formats for HDR (e.g. ARGB -> FP16) there are configurations that change from 2 pipes to 1 pipe. In these cases, it seems that disconnecting MPCC and doing a surface update at the same time(after unlocking) causes some registers to be updated slightly faster than others after unlocking (e.g. if the pixel format is updated to FP16 before the new surface address is programmed, we get corruption on the screen because the pixel formats aren't matching). We separate disconnecting MPCC from the rest of the pipe programming sequence to prevent this. [How] Move MPCC disconnect into separate operation than the rest of the pipe programming. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-04drm/amd/display: Fix logger contextHarry Wentland
[Why&How] use correct logger context Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-30drm/amd/display: Allow asic specific FSFT timing optimizationReza Amini
[Why] Each asic can optimize best based on its capabilities [How] Optimizing timing for a new pixel clock Signed-off-by: Reza Amini <Reza.Amini@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-27drm/amd/display: dce60_timing_generator: add DCE6 specific functions (v2)Mauro Rossi
[Why] DCE6 has CRTC_PREFETCH_EN bit in CRTC_CONTROL register DCE6 has no CRTC_LEGACY_REQUESTOR_EN bit in CRTC_START_LINE_CONTROL register DCE6 has no CRTC_CRC_CNTL register [How] Modify dce60_timing_generator_enable_advanced_request() function Add dce60_configure_crc() function and dce60_is_tg_enabled() kept as static Use dce60_configure_crc() function in dce60_tg_funcs v2: remove unused variable (Alex) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-27drm/amd/display: Rename bytes_pp to the correct bits_ppEryk Brol
[Why] Struct dcn_dsc_state is used for reading current state and parameters of DSC on a pipe, the target rate parameter uses bytes per pixel even though its reading BITS_PER_PIXEL register. [How] Changing it to Bits Per Pixel for consistency. Signed-off-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/display: Make new dc interface for adding dsc resourceAurabindo Pillai
[Why] dcn20_add_dsc_to_stream_resource is accessed in amdgpu_dm directly. This creates build error for configuration with DCN disabled. [How] Make the function available through a resource pool function so that dcn20 function need not be called directly. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/display: Add DSC parameters logging to debugfsEryk Brol
[why] Need to add new parameters to debugfs logging so we will know what parameters DSC is using for debug purposes. So we are adding a read function in debugfs to read DSC status registers Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-14drm/amd/display: reduce sr_xxx_time by 3 us when ppt disableChiawen Huang
[Why] when ppt disabled, the watermark doesn't get fine tune causing underflow. [How] It is a temporary solution to reduce sr_xxx_time by 3 us when ppt disable. Signed-off-by: Chiawen Huang <chiawen.huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-14drm/amd/display: Power down hardware if set mode is not called before timeoutSung Lee
[WHY] In headless systems, if set mode is not called, hardware will not be powered down on boot, causing HW/SW discrepancies. Powering down hardware on boot will ensure SW state is accurate. [HOW] Set a timer callback on boot for 10 seconds. If set mode is not called within that time, power down hardware. Otherwise, do not power down. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amd/display: Request PHYCLK adjustment on PHY enable/disableJoshua Aberback
[Why] Currently we don't explicitly send a request for a minimum PHYCLK, and we hope that the dependencies other clocks have will raise PHYCLK when needed. [How] - new clk_mgr function to keep track of PHYCLK requirements - request maximum requirement across all links - remove PHYCLK from clock state comparator, as it doesn't come from DML Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-02drm/amd/display: Preserve gpu memory allocation for life of dcJoshua Aberback
[Why] We want to keep the same buffer allocated for use during multiple hardware initializations. [How] - allocate gpu memory buffer on clock manager construct - free gpu memory buffer on clock manager destruct Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: DP link layer test 4.2.1.1 fix due to specs updateWenjing Liu
[why] DP link layer CTS specs updated to change the test parameters in test 4.2.1.1. Before it requires source to delay 400us on aux no reply. With the specs updates Errata5, it requires source to delay 3.2ms (based on LTTPR aux timeout) This causes our test to fail after updating with the latest test equipment firmware. [how] the change is to allow LTTPR 3.2ms aux timeout delay by default. And set back to 400us if LTTPR feature is not enabled. We will set 3.2ms and always enable LTTPR non transparent mode if LTTPR feature is enabled and LTTPR is present. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: make calculate watermarks a function pointerDmytro Laktyushkin
To allow code reuse with minimal duplication watermark calculation needs to be function pointer. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add helper to convert DC statusRodrigo Siqueira
During the debugging process related to a hot-plug problem with 4k display, we realized that we had some issues related to the global state validation. This problem was not explicitly highlighted in the dmesg log, for this reason, this commit adds a function that converts `enum dc_status` to a human-readable string and appends the proper warning message in case of failure. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: add support for per-state dummy-pstate latencyJun Lei
[why] Dummy pstate latency actually varies between different UCLK frequencies, when calculating watermark C, if DAL always assumes worst case, then it can lead to dummy pstate not supported scenarios. [how] Rather than statically calculating dummy pstate using worst case, we store the entire table of UCLK to dummy pstate relationships. On a per mode basis, we calculate the actual UCLK lower limit, and use the dynamic worst case dummy pstate latency. This prevents the situation where we don't support full p-state (which will force high DPM), but still use low DPM dummy pstate latency. Signed-off-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Revert "DP link layer test 4.2.1.1 fix due to specs update"Wenjing Liu
[why] The change causes some regression in a common use case. Will need more investigation before fixing the original issue. [how] This reverts commit fb8cf277b16d3f8b16941d217f7bae4ed7e73bea. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 ResourceBhawanpreet Lakha
Add support for managing resources for DCN3 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 HWSEQBhawanpreet Lakha
Add HW sequence programing for DCN3 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 DWBBhawanpreet Lakha
Add support to program the DCN3 DWB (Display Writeback) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ | | OPP | | +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 MMHUBHUBBhawanpreet Lakha
Add support to program the DCN3 MMHUBBUB (Multimedia HUB interface) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 HUBPBhawanpreet Lakha
Add support to program the DCN3 HUBP (Display to data fabric interface pipe) HW Blocks: +--------++------+ | HUBBUB || HUBP | +--------++------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 HUBHUBBhawanpreet Lakha
Add support to program the HUBBUB (DCN memory HUB interface) HW Blocks: +--------+ | HUBBUB | +--------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 DPPBhawanpreet Lakha
Add support to program the DCN3 DPP (Multiple pipe and plane combine) HW Blocks: +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 MPCBhawanpreet Lakha
Add support to program the DCN3 MPC (Multiple pipe and plane combine) HW Blocks: +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 OPTCBhawanpreet Lakha
Add support for programming the DCN3 OPTC (Output Timing Controller) HW Blocks: +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-30 12:27:21 +0000