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path: root/drivers/clk/qcom/dispcc-sm8250.c
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2025-02-14clk: qcom: Add missing header includesKrzysztof Kozlowski
Include mod_devicetable.h for the 'struct of_device_id' and clk-provider.h for the 'struct clk_hw'. Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250212-b4-clk-qcom-clean-v3-3-499f37444f5d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-14clk: qcom: Drop unused header includesKrzysztof Kozlowski
Drivers should include only headers they use so drop: 1. of.h and of_address.h: When no OF call is used (of_device_id is coming from mod_devicetable.h). 2. clk.h, property.h and reset-controller.h: No calls to clock consumer or reset framework, no fwnode/property calls. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250212-b4-clk-qcom-clean-v3-2-499f37444f5d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLLDmitry Baryshkov
According to msm-5.10 the lucid 5lpe PLLs have require slightly different configuration that trion / lucid PLLs, it doesn't set PLL_UPDATE_BYPASS bit. Add corresponding function and use it for the display clock controller on Qualcomm SM8350 platform. Fixes: 205737fe3345 ("clk: qcom: add support for SM8350 DISPCC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-2-1149dd8399fe@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocksDmitry Baryshkov
Add CLK_SET_RATE_PARENT for several branch clocks. Such clocks don't have a way to change the rate, so set the parent rate instead. Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250") Cc: stable@vger.kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-1-1149dd8399fe@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12clk: qcom: common: commonize qcom_cc_really_probeLuo Jie
The previous wrapper qcom_cc_really_probe takes the platform device as parameter, which is limited to platform driver. As for qca8k clock controller driver, which is registered as the MDIO device, which also follows the qcom clock framework. To commonize qcom_cc_really_probe, updating it to take the struct device as parameter, so that the qcom_cc_really_probe can be utilized by the previous platform device and the new added MDIO device. Also update the current clock controller drivers to take &pdev->dev as parameter when calling qcom_cc_really_probe. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240605124541.2711467-4-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14clk: qcom: Use qcom_branch_set_clk_en()Konrad Dybcio
Instead of magically poking at the bit0 of branch clocks' CBCR, use the newly introduced helper. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240212-topic-clk_branch_en-v7-2-5b79eb7278b2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: dispcc-sm8250: Make clk_init_data and pll_vco constSatya Priya Kakitapalli
The clk_init_data and pll_vco structures are never modified, make them const. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240201-dispcc-sm8150-v1-1-cbeb89015e5d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: dispcc-*: switch to module_platform_driverDmitry Baryshkov
There is no need to register display clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240206-clk-module-platform-driver-v1-2-db799bd2feeb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-01-10clk: qcom: dispcc-sm8250: switch to devm_pm_runtime_enableDmitry Baryshkov
Switch to using the devm_pm_runtime_enable() instead of hand-coding corresponding action to call pm_runtime_disable(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103145515.1164020-19-dmitry.baryshkov@linaro.org
2022-11-05clk: qcom: dispcc-sm8250: Disable link_div_clk_src for sm8150Robert Foss
SM8150 does not have any of the link_div_clk_src clocks, so let's disable them for this SoC. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102090140.965450-6-robert.foss@linaro.org
2022-11-05clk: qcom: dispcc-sm8250: Add missing EDP clocks for sm8350Robert Foss
SM8350 supports embedded displayport, but the clocks for this were previously not accounted for. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102090140.965450-5-robert.foss@linaro.org
2022-11-05clk: qcom: dispcc-sm8250: Add RETAIN_FF_ENABLE flag for mdss_gdscRobert Foss
All SoC supported by this driver supports the RETAIN_FF_ENABLE flag, so it should be enabled here. This feature enables registers to maintain their state after dis/re-enabling the GDSC. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102090140.965450-3-robert.foss@linaro.org
2022-11-05clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350Robert Foss
SM8350 does not have the EDP_GTC clock, so let's disable it for this SoC. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102090140.965450-2-robert.foss@linaro.org
2022-07-18clk: qcom: Drop mmcx gdsc supply for dispcc and videoccAbel Vesa
Both dispcc and videocc use mmcx power domain now. Lets drop the supply mmcx from every gdsc. Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: 266e5cf39a0f ("arm64: dts: qcom: sm8250: remove mmcx regulator") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220713143200.3686765-1-abel.vesa@linaro.org
2022-07-06clk: qcom: add support for SM8350 DISPCCJonathan Marek
Add support to the SM8350 display clock controller by extending the SM8250 display clock controller, which is almost identical but has some minor differences. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706154337.2026269-5-robert.foss@linaro.org
2022-02-24clk: qcom: dispcc: Update the transition delay for MDSS GDSCTaniya Das
On SC7180 we observe black screens because the gdsc is being enabled/disabled very rapidly and the GDSC FSM state does not work as expected. This is due to the fact that the GDSC reset value is being updated from SW. The recommended transition delay for mdss core gdsc updated for SC7180/SC7280/SM8250. Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC7180") Fixes: 1a00c962f9cd ("clk: qcom: Add display clock controller driver for SC7280") Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/20220223185606.3941-2-tdas@codeaurora.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sboyd@kernel.org: lowercase hex] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: dispcc-sm8250: use runtime PM for the clock controllerDmitry Baryshkov
On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829154757.784699-4-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-07-27clk: qcom: dispcc-sm8250: Add additional parent clocks for DPBjorn Andersson
The clock controller has two additional clock source pairs, in order to support more than a single DisplayPort PHY. List these, so it's possible to describe them all. Also drop the unnecessary freq_tbl for the link clock sources, to allow these parents to be used. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210721224610.3035258-1-bjorn.andersson@linaro.org Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: qcom: dispcc-sm8250: Add EDP clocksBjorn Andersson
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210511041719.591969-2-bjorn.andersson@linaro.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: qcom: dispcc-sm8250: Add sc8180x supportBjorn Andersson
The display clock controller in SC8180x is reused from SM8150, so add the necessary compatible and wire up the driver to enable this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210511041719.591969-1-bjorn.andersson@linaro.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-04-07clk: qcom: dispcc-sm8250: use parent_hws where possibleDmitry Baryshkov
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210405224743.590029-19-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-04-07clk: qcom: dispcc-sm8250: drop unused enum entriesDmitry Baryshkov
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210405224743.590029-3-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-14clk: qcom: dispcc-sm8250: handle MMCX power domainDmitry Baryshkov
On SM8250 MMCX power domain is required to access MMDS_GDSC registers. This power domain is expressed as mmcx-supply regulator property. Use this regulator as MDSS_GDSC supply. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20201023131925.334864-6-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: qcom: Add display clock controller driver for SM8150 and SM8250Jonathan Marek
Add support for the display clock controller found on SM8150 and SM8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Link: https://lore.kernel.org/r/20200927190653.13876-3-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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