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path: root/drivers/accel/qaic/qaic.h
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2025-06-06accel/qaic: delete qaic_bo.handleSimona Vetter
Handles are per-file, not global, so this makes no sense. Plus it's set only after calling drm_gem_handle_create(), and drivers are not allowed to further initialize a bo after that function has published it already. It is also entirely unused, which helps enormously with removing it :-) Since we're still holding a reference to the bo nothing bad can happen, hence not cc: stable material. Cc: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Cc: Carl Vanderlip <quic_carlv@quicinc.com> Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> Signed-off-by: Simona Vetter <simona.vetter@intel.com> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250528091307.1894940-5-simona.vetter@ffwll.ch
2025-05-30accel/qaic: Add Reliability, Accessibility, Serviceability (RAS)Jeff Hugo
AIC100 devices generates Reliability, Availability, Serviceability events via MHI QAIC_STATUS channel. Support such events and print a structured log with details of the events, and if the event describes an uncorrected error, reset the device to put it back into service. As these events may not all be reported via other mechanisms like AER, maintain counts of the number of errors observed for each type. Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Reviewed-by: Troy Hanson <quic_thanson@quicinc.com> Reviewed-by: Maciej Falkowski <maciej.falkowski@linux.intel.com> Link: https://lore.kernel.org/r/20250516160634.1408309-1-jeff.hugo@oss.qualcomm.com
2025-01-31accel/qaic: Add AIC200 supportJeffrey Hugo
Add basic support for the new AIC200 product. The PCIe Device ID is 0xa110. With this, we can turn on the lights for AIC200 by leveraging much of the existing driver. Co-developed-by: Youssef Samir <quic_yabdulra@quicinc.com> Signed-off-by: Youssef Samir <quic_yabdulra@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Lizhi Hou <lizhi.hou@amd.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250117170943.2643280-8-quic_jhugo@quicinc.com
2025-01-31accel/qaic: Add config structs for supported cardsJeffrey Hugo
As the number of cards supported by the driver grows, their configurations will differ. The driver needs to become more dynamic to support these configurations. Currently, each card may differ in the exposed BARs, the regions they map to, and the family. Create config structs for each card, and let the driver configure the qaic_device struct based on the configurations passed to the driver. Co-developed-by: Youssef Samir <quic_yabdulra@quicinc.com> Signed-off-by: Youssef Samir <quic_yabdulra@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250117170943.2643280-7-quic_jhugo@quicinc.com
2024-04-05accel/qaic: Add fifo queued debugfsJeffrey Hugo
When debugging functional issues with workload input processing, it is useful to know if requests are backing up in the fifo, or perhaps getting stuck elsewhere. To answer the question of how many requests are in the fifo, implement a "queued" debugfs entry per-dbc that returns the number of pending requests when read. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240322175730.3855440-4-quic_jhugo@quicinc.com
2024-04-05accel/qaic: Add bootlog debugfsJeffrey Hugo
During the boot process of AIC100, the bootloaders (PBL and SBL) log messages to device RAM. During SBL, if the host opens the QAIC_LOGGING channel, SBL will offload the contents of the log buffer to the host, and stream any new messages that SBL logs. This log of the boot process can be very useful for an initial triage of any boot related issues. For example, if SBL rejects one of the runtime firmware images for a validation failure, SBL will log a reason why. Add the ability of the driver to open the logging channel, receive the messages, and store them. Also define a debugfs entry called "bootlog" by hooking into the DRM debugfs framework. When the bootlog debugfs entry is read, the current contents of the log that the host is caching is displayed to the user. The driver will retain the cache until it detects that the device has rebooted. At that point, the cache will be freed, and the driver will wait for a new log. With this scheme, the driver will only have a cache of the log from the current device boot. Note that if the driver initializes a device and it is already in the runtime state (QSM), no bootlog will be available through this mechanism because the driver and SBL have not communicated. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240322175730.3855440-2-quic_jhugo@quicinc.com
2023-12-20accel/qaic: Leverage DRM managed APIs to release resourcesPranjal Ramajor Asha Kanojiya
Offload the balancing of init and destroy calls to DRM managed APIs. mutex destroy for ->cntl_mutex is not called during device release and destroy workqueue is not called in error path of create_qdev(). So, use DRM managed APIs to manage the release of resources and avoid such problems. Signed-off-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231208163457.1295993-7-quic_jhugo@quicinc.com
2023-12-15accel/qaic: Remove bo->queued fieldPranjal Ramajor Asha Kanojiya
->queued field is used to track whether the BO is submitted to hardware for DMA or not. Since same information can be retrieved using ->xfer_list field of same structure remove ->queued as it is redundant. Signed-off-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231208163457.1295993-3-quic_jhugo@quicinc.com
2023-12-01accel/qaic: Expand DRM device lifecycleCarl Vanderlip
Currently the QAIC DRM device registers itself when the MHI QAIC_CONTROL channel becomes available. This is when the device is able to process workloads. However, the DRM driver also provides the debugfs interface bootlog for the device. If the device fails to boot to the QSM (which brings up the MHI QAIC_CONTROL channel), the bootlog won't be available for debugging why it failed to boot. Change when the DRM device registers itself from when QAIC_CONTROL is available to when the card is first probed on the PCI bus. Additionally, make the DRM driver persist through reset/error cases so the driver doesn't have to be reloaded to access the card again. Send KOBJ_ONLINE/OFFLINE uevents so userspace can know when DRM device is ready to handle requests. Signed-off-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231117174337.20174-3-quic_jhugo@quicinc.com
2023-12-01accel/qaic: Increase number of in_reset statesCarl Vanderlip
'in_reset' holds the state of the device. As part of bringup, the device needs to be queried to check if it's in a valid state. Add a new state that indicates that the device is coming up, but not ready for users yet. Rename to 'dev_state' to better describe the variable. Signed-off-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231117174337.20174-2-quic_jhugo@quicinc.com
2023-10-27accel/qaic: Support MHI QAIC_TIMESYNC channelPranjal Ramajor Asha Kanojiya
Use QAIC_TIMESYNC MHI channel to send UTC time to device in SBL environment. Remove support for QAIC_TIMESYNC MHI channel in AMSS environment as it is not used in that environment. Signed-off-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231016170114.5446-3-quic_jhugo@quicinc.com
2023-10-27accel/qaic: Enable 1 MSI fallback modeCarl Vanderlip
Several virtualization use-cases either don't support 32 MultiMSIs (Xen/VMware) or have significant drawbacks to their use (KVM's vIOMMU, which is required to support 32 MSI, needs to allocate an alternate system memory space for each device using vIOMMU (e.g. 8GB VM mem and 2 cards => 8 + 2 * 8 = 24GB host memory required)). Support these cases by enabling a 1 MSI fallback mode. Whenever all 32 MSIs requested are not available, a second request for a single MSI is made. Its success is the initiator of single MSI mode. This mode causes all interrupts generated by the device to be directed to the 0th MSI (firmware >=v1.10 will do this as a response to the PCIe MSI capability configuration). Likewise, all interrupt handlers for the device are registered to the 0th MSI. Since the DBC interrupt handler checks if the DBC is in use or if there is any pending changes, the 'spurious' interrupts are disregarded. If there is work to be done, the standard threaded IRQ handler is dispatched. On every interrupt, the MHI handler wakes up its threaded interrupt handler, and attempts to wake any waiters for MHI state events. Performance is within +-0.6% for test cases that typify real world use. Larger differences ([-4,+132]%, avg +47%) exist for very simple tasks (e.g. addition) compiled for single NSPs. It is assumed that the small work and many interrupts typically cause contention (e.g. 16 NSPs vs 4 CPUs), as evidenced by the standard deviation between runs also decreasing (r=-0.48 between delta(Performace_test) and delta(StdDev_test/Avg_test)) Signed-off-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231016170036.5409-1-quic_jhugo@quicinc.com
2023-09-22accel/qaic: Add QAIC_DETACH_SLICE_BO IOCTLPranjal Ramajor Asha Kanojiya
Once a BO is attached with slicing configuration that BO can only be used for that particular setting. With this new feature user can detach slicing configuration off an already sliced BO and attach new slicing configuration using QAIC_ATTACH_SLICE_BO. This will support BO recycling. detach_slice_bo() detaches slicing configuration from a BO. This new helper function can also be used in release_dbc() as we are doing the exact same thing. Signed-off-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> [jhugo: add documentation for new ioctl] Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230901172247.11410-8-quic_jhugo@quicinc.com
2023-09-22accel/qaic: Remove ->size field from struct qaic_boPranjal Ramajor Asha Kanojiya
->size field in struct qaic_bo stores user requested buffer size for allocate path or size of the dmabuf(PRIME). Now for allocate path driver allocates a BO of size which is PAGE_SIZE aligned, this size is already stored in base BO structure (struct drm_gem_object). So difference is ->size of struct qaic_bo stores the raw value coming from user and ->size in struct drm_gem_object stores the PAGE_SZIE aligned size. Do not use ->size from struct qaic_bo for any validation or operation instead use ->size from struct drm_gem_object since we already have allocated that much memory then why not use it. Only validate if user is trying to use more then the BO size. This make the driver more flexible. After this change ->size field of struct qaic_bo becomes redundant. Remove it. Signed-off-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230901172247.11410-2-quic_jhugo@quicinc.com
2023-09-15accel/qaic: Use devm_drm_dev_alloc() instead of drm_dev_alloc()Pranjal Ramajor Asha Kanojiya
Since drm_dev_alloc() is deprecated it is recommended to use devm_drm_dev_alloc() instead. Update the driver to start using devm_drm_dev_alloc(). Signed-off-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230901161236.8371-1-quic_jhugo@quicinc.com
2023-04-06accel/qaic: Add uapi and core driver fileJeffrey Hugo
Add the QAIC driver uapi file and core driver file that binds to the PCIe device. The core driver file also creates the accel device and manages all the interconnections between the different parts of the driver. The driver can be built as a module. If so, it will be called "qaic.ko". Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Acked-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1679932497-30277-3-git-send-email-quic_jhugo@quicinc.com