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path: root/arch/x86/kernel
AgeCommit message (Expand)Author
14 daysx86/rdrand: Disable RDSEED on AMD Cyan SkillfishMikhail Paulyshka
14 daysx86/mce: Make sure CMCI banks are cleared during shutdown on IntelJP Kobryn
14 daysx86/mce: Ensure user polling settings are honored when restarting timerYazen Ghannam
14 daysx86/mce: Don't remove sysfs if thresholding sysfs init failsYazen Ghannam
14 daysx86/mce/amd: Fix threshold limit resetYazen Ghannam
14 daysx86/mce/amd: Add default names for MCA banks and blocksYazen Ghannam
2025-07-14x86/CPU/AMD: Properly check the TSA microcodeBorislav Petkov (AMD)
2025-07-10x86/process: Move the buffer clearing before MONITORBorislav Petkov (AMD)
2025-07-10x86/microcode/AMD: Add TSA microcode SHAsBorislav Petkov (AMD)
2025-07-10x86/bugs: Add a Transient Scheduler Attacks mitigationBorislav Petkov (AMD)
2025-07-10x86/bugs: Rename MDS machinery to something more genericBorislav Petkov (AMD)
2025-07-06x86/pkeys: Simplify PKRU update in signal frameChang S. Bae
2025-07-06x86/fpu: Refactor xfeature bitmask update code for sigframe XSAVEChang S. Bae
2025-07-06x86/traps: Initialize DR6 by writing its architectural reset valueXin Li (Intel)
2025-06-27x86/sgx: Prevent attempts to reclaim poisoned pagesAndrew Zaborowski
2025-06-19x86/fred/signal: Prevent immediate repeat of single step trap on return from ...Xin Li (Intel)
2025-06-19x86/iopl: Cure TIF_IO_BITMAP inconsistenciesThomas Gleixner
2025-06-19x86/irq: Ensure initial PIR loads are performed exactly onceSean Christopherson
2025-06-19x86/mtrr: Check if fixed-range MTRRs exist in mtrr_save_fixed_ranges()Jiaqing Zhao
2025-06-19x86/cpu: Sanitize CPUID(0x80000000) outputAhmed S. Darwish
2025-06-19x86/microcode/AMD: Do not return error when microcode update is not necessaryAnnie Li
2025-06-19x86/idle: Remove MFENCEs for X86_BUG_CLFLUSH_MONITOR in mwait_idle_with_hints...Andrew Cooper
2025-05-29x86/traps: Cleanup and robustify decode_bug()Peter Zijlstra
2025-05-29x86/ibt: Handle FineIBT in handle_cfi_failure()Peter Zijlstra
2025-05-29x86/nmi: Add an emergency handler in nmi_desc & use it in nmi_shootdown_cpus()Waiman Long
2025-05-29x86/bugs: Make spectre user default depend on MITIGATION_SPECTRE_V2Breno Leitao
2025-05-29x86/microcode: Update the Intel processor flag scan checkSohil Mehta
2025-05-29x86/smpboot: Fix INIT delay assignment for extended Intel FamiliesSohil Mehta
2025-05-18x86/its: FineIBT-paranoid vs ITSPeter Zijlstra
2025-05-18x86/its: Fix build errors when CONFIG_MODULES=nEric Biggers
2025-05-18x86/its: Use dynamic thunks for indirect branchesPeter Zijlstra
2025-05-18x86/ibt: Keep IBT disabled during alternative patchingPawan Gupta
2025-05-18x86/its: Add support for RSB stuffing mitigationPawan Gupta
2025-05-18x86/its: Add "vmexit" option to skip mitigation on some CPUsPawan Gupta
2025-05-18x86/its: Enable Indirect Target Selection mitigationPawan Gupta
2025-05-18x86/its: Add support for ITS-safe return thunkPawan Gupta
2025-05-18x86/its: Add support for ITS-safe indirect thunkPawan Gupta
2025-05-18x86/its: Enumerate Indirect Target Selection (ITS) bugPawan Gupta
2025-05-18x86/bhi: Do not set BHI_DIS_S in 32-bit modePawan Gupta
2025-05-18x86/bpf: Add IBHF call at end of classic BPFDaniel Sneddon
2025-05-18x86/microcode: Consolidate the loader enablement checkingBorislav Petkov (AMD)
2025-05-02x86/i8253: Call clockevent_i8253_disable() with interrupts disabledFernando Fernandez Mancera
2025-05-02x86/bugs: Don't fill RSB on context switch with eIBRSJosh Poimboeuf
2025-05-02x86/bugs: Don't fill RSB on VMEXIT with eIBRS+retpolineJosh Poimboeuf
2025-04-25x86/cpu/amd: Fix workaround for erratum 1054Sandipan Das
2025-04-25x86/microcode/AMD: Extend the SHA check to Zen5, block loading of any unrelea...Borislav Petkov (AMD)
2025-04-20x86/e820: Fix handling of subpage regions when calculating nosave ranges in e...Myrrh Periwinkle
2025-04-20x86/paravirt: Move halt paravirt calls under CONFIG_PARAVIRTKirill A. Shutemov
2025-04-20x86/cpu: Don't clear X86_FEATURE_LAHF_LM flag in init_amd_k8() on AMD when ru...Max Grobecker
2025-04-20x86/ia32: Leave NULL selector values 0~3 unchangedXin Li (Intel)