linux/linux-stable.git - Linux kernel stable tree

Age	Commit message (Expand)	Author
8 days	mm: remove arch_flush_tlb_batched_pending() arch helper	Ryan Roberts
2025-06-05	riscv: Add support for PUD THP	Alexandre Ghiti
2025-03-16	mm: support tlbbatch flush for a range of PTEs	Barry Song
2024-04-29	riscv: mm: Use a fixed layout for the MM context ID	Samuel Holland
2024-04-29	riscv: Avoid TLB flush loops when affected by SiFive CIP-1200	Samuel Holland
2024-04-29	riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma	Samuel Holland
2024-04-29	riscv: mm: Combine the SMP and UP TLB flush code	Samuel Holland
2024-01-31	riscv: mm: execute local TLB flush after populating vmemmap	Vincent Chen
2024-01-20	Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds
2024-01-11	riscv: Add support for BATCHED_UNMAP_TLB_FLUSH	Alexandre Ghiti
2023-12-14	mm: Introduce flush_cache_vmap_early()	Alexandre Ghiti
2023-11-06	riscv: Improve flush_tlb_kernel_range()	Alexandre Ghiti
2023-11-06	riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb	Alexandre Ghiti
2023-11-06	riscv: Improve tlb_flush()	Alexandre Ghiti
2023-03-21	riscv: mm: Fix incorrect ASID argument when flushing TLB	Dylan Jhong
2023-03-09	Revert "riscv: mm: notify remote harts about mmu cache updates"	Sergey Matyukevich
2022-12-08	riscv: mm: notify remote harts about mmu cache updates	Sergey Matyukevich
2021-06-08	riscv: fix build error when CONFIG_SMP is disabled	Bixuan Cui
2021-04-26	riscv: sifive: Apply errata "cip-1200" patch	Vincent Chen
2019-11-17	riscv: add nommu support	Christoph Hellwig
2019-10-14	riscv: tlbflush: remove confusing comment on local_flush_tlb_all()	Paul Walmsley
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig
2019-08-13	riscv: fix flush_tlb_range() end address for flush_tlb_page()	Paul Walmsley
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner
2018-10-22	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra
2018-06-07	riscv: use NULL instead of a plain 0	Luc Van Oostenryck
2018-01-30	RISC-V: Limit the scope of TLB shootdowns	Andrew Waterman
2018-01-07	riscv: remove CONFIG_MMU ifdefs	Christoph Hellwig
2017-12-01	RISC-V: User-Visible Changes	Palmer Dabbelt
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman
2017-11-28	RISC-V: `sfence.vma` orderes the instruction cache	Palmer Dabbelt
2017-09-26	RISC-V: Atomic and Locking Code	Palmer Dabbelt