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2025-07-10arm64: dts: st: remove empty line in stm32mp251.dtsiPatrick Delaunay
Remove unnecessary empty line in stm32mp251.dtsi Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250515151238.2.Ia426b4ef1d1200247a950ef9abd54a94dc520acb@changeid Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-10arm64: dts: st: fix timer used for ticksPatrick Delaunay
Remove always-on on generic ARM timer as the clock source provided by STGEN is deactivated in low power mode, STOP1 by example. Fixes: 5d30d03aaf78 ("arm64: dts: st: introduce stm32mp25 SoCs family") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250515151238.1.I85271ddb811a7cf73532fec90de7281cb24ce260@changeid Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04arm64: dts: st: add timer nodes on stm32mp257f-ev1Fabrice Gasnier
Configure timer nodes on stm32mp257f-ev1: - Timer3 CH2 is available on mikroBUS connector for PWM - timer8 CH1, timer8 CH4, timer10 CH1 and timer12 CH2 are available on EXPANSION connector. Timers are kept disabled by default, so the pins can be used for any other purpose (and the timers can be assigned to any of the processors). Arbitrary choice is to use all these timers as PWM (or counter on internal clock signal), except for timer10 that is configured with CH1 as an input (for capture). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-9-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04arm64: dts: st: add timer pins for stm32mp257f-ev1Fabrice Gasnier
Add timer pins available on stm32mp257f-ev1, configured for PWM: - timer3 CH2 is available on mikroBUS connector - timer8 CH1, timer8 CH4, timer10 CH1 and timer12 CH2 are available on EXPANSION connector Arbitrary define all these pins to be used as PWM (output) channels, except for timer10 CH1, to be used as counter input. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-8-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04arm64: dts: st: add timer nodes on stm32mp251Fabrice Gasnier
Add timers support on STM32MP25 SoC. Use dedicated compatible to handle new features and instances introduced with this SoC. STM32MP25 SoC has various timer flavours, each group has its own specific feature list: - Advanced-control timers (TIM1/TIM8/TIM20) - General-purpose timers (TIM2/TIM3/TIM4/TIM5) - Basic timers (TIM6/TIM7) - General-purpose timers (TIM10/TIM11/TIM12/TIM13/TIM14) - General purpose timers (TIM15/TIM16/TIM17) Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-7-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-31Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "There are 11 newly supported SoCs, but these are all either new variants of existing designs, or straight reuses of the existing chip in a new package: - RK3562 is a new chip based on the old Cortex-A53 core, apparently a low-cost version of the Cortex-A55 based RK3568/RK3566. - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different set of on-chip peripherals. - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family - Amlogic S6/S7/S7D - Samsung Exynos7870 is an older chip similar to Exynos7885 - WonderMedia wm8950 is a minor variation on the wm8850 chip - Amlogic s805y is almost idential to s805x - Allwinner A523 is similar to A527 and T527 - Qualcomm MSM8926 is a variant of MSM8226 - Qualcomm Snapdragon X1P42100 is related to R1E80100 There are also 65 boards, including reference designs for the chips above, this includes - 12 new boards based on TI K3 series chips, most of them from Toradex - 10 devices using Rockchips RK35xx and PX30 chips - 2 phones and 2 laptops based on Qualcomm Snapdragon designs - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses - 3 Samsung Galaxy phones based on Exynos7870 - 5 Allwinner based boards using a variety of ARMv8 chips - 9 32-bit machines, each based on a different SoC family Aside from the new hardware, there is the usual set of cleanups and newly added hardware support on existing machines, for a total of 965 devicetree changesets" * tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits) MAINTAINERS, mailmap: update Sven Peter's email address arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency arm64: dts: nuvoton: Add pinctrl ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings arm64: dts: blaize-blzp1600: Enable GPIO support dt-bindings: clock: socfpga: convert to yaml arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3562 pcie unit addresses arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3576 pcie unit addresses arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588 arm64: dts: rockchip: Add missing SFC power-domains to rk3576 Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0" arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes arm64: dts: mt6359: Rename RTC node to match binding expectations arm64: dts: mt8365-evk: Add goodix touchscreen support arm64: dts: mediatek: mt8188: Add missing #reset-cells property arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board ...
2025-05-14arm64: dts: st: use lptimer3 as tick broadcast source on stm32mp257f-ev1Fabrice Gasnier
During the low power modes the generic ARM timer is deactivated, so the the tick broadcast is used, based on LPTIMER3 which is clocked by LSE on STMicroelectronics boards. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: add low-power timer nodes on stm32mp251Fabrice Gasnier
Add low-power timer (LPTimer) support on STM32MP25 SoC. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features (no capture/compare) channel. Still, LPTIM5 can be used as single PWM, counter, trigger or timer. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250429125133.1574167-7-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: Add SPI NOR flash support on stm32mp257f-ev1 boardPatrice Chotard
Add SPI NOR flash nor support on stm32mp257f-ev1 board. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-3-fca0fbe6d10a@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: Add ospi port1 pinctrl entries in stm32mp25-pinctrl.dtsiPatrice Chotard
Add pinctrl entry related to OSPI's port1 in stm32mp25-pinctrl.dtsi Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-2-fca0fbe6d10a@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: Add OMM node on stm32mp251Patrice Chotard
Add Octo Memory Manager (OMM) entry on stm32mp251 and its two OSPI instance. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-1-fca0fbe6d10a@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-04-29arm64: dts: st: Use 128kB size for aliased GIC400 register access on ↵Christian Bruel
stm32mp23 SoCs Adjust the size of 8kB GIC regions to 128kB so that each 4kB is mapped 16 times over a 64kB region. The offset is then adjusted in the irq-gic driver. see commit 12e14066f4835 ("irqchip/GIC: Add workaround for aliased GIC400") Fixes: e9b03ef21386e ("arm64: dts: st: introduce stm32mp23 SoCs family") Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-7-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-04-29arm64: dts: st: Adjust interrupt-controller for stm32mp23 SoCsChristian Bruel
Use gic-400 compatible and remove address-cells = <1> for aarch64 Fixes: e9b03ef21386e ("arm64: dts: st: introduce stm32mp23 SoCs family") Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-6-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-04-29arm64: dts: st: Use 128kB size for aliased GIC400 register access on ↵Christian Bruel
stm32mp21 SoCs Adjust the size of 8kB GIC regions to 128kB so that each 4kB is mapped 16 times over a 64kB region. The offset is then adjusted in the irq-gic driver. see commit 12e14066f4835 ("irqchip/GIC: Add workaround for aliased GIC400") Fixes: 7a57b1bb1afbf ("arm64: dts: st: introduce stm32mp21 SoCs family") Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-5-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-04-29arm64: dts: st: Adjust interrupt-controller for stm32mp21 SoCsChristian Bruel
Use gic-400 compatible for aarch64 Fixes: 7a57b1bb1afbf ("arm64: dts: st: introduce stm32mp21 SoCs family") Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-4-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-04-29arm64: dts: st: Use 128kB size for aliased GIC400 register access on ↵Christian Bruel
stm32mp25 SoCs Adjust the size of 8kB GIC regions to 128kB so that each 4kB is mapped 16 times over a 64kB region. The offset is then adjusted in the irq-gic driver. see commit 12e14066f4835 ("irqchip/GIC: Add workaround for aliased GIC400") Fixes: 5d30d03aaf785 ("arm64: dts: st: introduce stm32mp25 SoCs family") Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250415111654.2103767-3-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-04-29arm64: dts: st: Adjust interrupt-controller for stm32mp25 SoCsChristian Bruel
Use gic-400 compatible and remove address-cells = <1> on aarch64 Fixes: 5d30d03aaf785 ("arm64: dts: st: introduce stm32mp25 SoCs family") Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-2-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-03-12arm64: dts: st: add stm32mp215f-dk board supportAmelie Delaunay
Add STM32MP215F Discovery Kit board support. It embeds a STM32MP235FAN SoC, with 2GB of LPDDR4, 1*USB2 peripheral bus powered typeC, 1*ETH, wifi/BT combo, LCD 18bit connector, CSI camera connector, ... Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-10-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-03-12arm64: dts: st: introduce stm32mp21 SoCs familyAlexandre Torgue
STM32MP21 family is composed of 3 SoCs defined as following: -STM32MP211: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP213: STM32MP211 + a second ETH, CAN-FD. -STM32MP215: STM32MP213 + Display and CSI2. A second diversity layer exists for security features/ A35 frequency: -STM32MP21xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-8-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-03-12arm64: dts: st: add stm32mp235f-dk board supportAmelie Delaunay
Add STM32MP235F Discovery Kit board support. It embeds a STM32MP235FAK SoC, with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ... Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-7-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-03-12arm64: dts: st: introduce stm32mp23 SoCs familyAlexandre Torgue
STM32MP23 family is composed of 3 SoCs defined as following: -STM32MP231: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP233: STM32MP231 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD. -STM32MP235: STM32MP233 + GPU/AI and video encode/decode, DSI and LDVS display. A second diversity layer exists for security features/ A35 frequency: -STM32MP23xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-5-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-03-12arm64: dts: st: add stm32mp257f-dk board supportAlexandre Torgue
Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC, with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ... Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-2-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20arm64: dts: st: enable imx335/csi/dcmipp pipeline on stm32mp257f-ev1Alain Volmat
Enable the camera pipeline with a imx335 sensor connected to the dcmipp via the csi interface. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20arm64: dts: st: add csi & dcmipp node in stm32mp25Alain Volmat
Add nodes describing the csi and dcmipp controllers handling the camera pipeline on the stm32mp25x. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: Enable COMBOPHY on the stm32mp257f-ev1 boardChristian Bruel
Enable the COMBOPHY with external pad clock on stm32mp257f-ev1 board, to be used for the PCIe clock provider. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: Add combophy node on stm32mp251Christian Bruel
Add support for COMBOPHY which is used either by the USB3 and PCIe controller. USB3 or PCIe mode is done with phy_set_mode(). PCIe internal reference clock can be generated from the internal clock source or optionnaly from an external 100Mhz pad. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: add spdifrx support on stm32mp251Olivier Moysan
Add S/PDIFRX support to STM32MP25 SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: add sai support on stm32mp251Olivier Moysan
Add SAI support to STM32MP25 SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: add i2s support to stm32mp251Olivier Moysan
Add I2S support to STM32MP25 SoCs. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29arm64: dts: st: add DMA support on SPI instances of stm32mp25Amelie Delaunay
Add dmas and dma-names properties in spi nodes of stm32mp251.dtsi to enable DMA support. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29arm64: dts: st: add DMA support on I2C instances of stm32mp25Amelie Delaunay
Add dmas and dma-names properties in i2c nodes of stm32mp251.dtsi to enable DMA support. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29arm64: dts: st: add DMA support on U(S)ART instances of stm32mp25Amelie Delaunay
Add dmas and dma-names properties in u(s)art nodes of stm32mp251.dtsi to enable DMA support. RX channel requires to prevent pack/unpack feature of DMA to avoid losing bytes when interrupting RX transfer, as it uses a cyclic buffer. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29arm64: dts: st: add RNG node on stm32mp251Gatien Chevallier
Update the device-tree stm32mp251.dtsi by adding the Random Number Generator(RNG) node. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29arm64: dts: st: enable RTC on stm32mp257f-ev1 boardValentin Caron
Enable RTC on stm32mp257f-ev1 board. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29arm64: dts: st: add RTC on stm32mp25xValentin Caron
Add compatible, clock, and interrupt properties of STM32 RTC on stm32mp25x SOCs. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-07-05arm64: dts: st: describe power supplies for stm32mp257f-ev1 boardPascal Paillet
Describe power supplies for stm32mp257f-ev1 board. Signed-off-by: Pascal Paillet <p.paillet@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-07-05arm64: dts: st: add scmi regulators on stm32mp25Pascal Paillet
Add SCMI regulators description on STM32MP25. Signed-off-by: Pascal Paillet <p.paillet@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-07-05arm64: dts: st: enable Ethernet2 on stm32mp257f-ev1 boardChristophe Roullier
ETHERNET2 instance is connected to Realtek PHY in RGMII mode Ethernet is SNSP IP with GMAC5 version. Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-07-05arm64: dts: st: add eth2 pinctrl entries in stm32mp25-pinctrl.dtsiChristophe Roullier
Add pinctrl entry related to ETH2 in stm32mp25-pinctrl.dtsi ethernet2: RGMII with crystal. Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-07-05arm64: dts: st: add ethernet1 and ethernet2 support on stm32mp25Christophe Roullier
Both instances ethernet based on GMAC SNPS IP on stm32mp25. GMAC IP version is SNPS 5.3 Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-07-05arm64: dts: st: add HPDMA nodes on stm32mp251Amelie Delaunay
The High Performance Direct Memory Access (HPDMA) controller is used to perform programmable data transfers between memory-mapped peripherals and memories (or between memories) via linked-lists. There are 3 instances of HPDMA on stm32mp251, using stm32-dma3 driver, with 16 channels per instance and with one interrupt per channel. Channels 0 to 7 are implemented with a FIFO of 8 bytes. Channels 8 to 11 are implemented with a FIFO of 32 bytes. Channels 12 to 15 are implemented with a FIFO of 128 bytes. Thanks to stm32-dma3 bindings, the user can ask for a channel with specific FIFO size. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-06-05arm64: dts: st: add power domain on stm32mp25Patrick Delaunay
Add power domains on STM32MP25x SoC for supported low power modes: - CPU_PD0/1: domain for idle of each core Cortex A35 (CStop) - CLUSTER_PD: D1 domain with Stop1 and LP-Stop1 modes support when the Cortex A35 cluster and each device assigned to CPU1=CA35 are deactivated - RET_PD: D1 domain retention (VDDCore is reduced) to support the LPLV-Stop1 mode Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-06-05arm64: dts: st: add usart6 on stm32mp257f-ev1 boardValentin Caron
Add node for USART6 on stm32mp257f-ev1 board. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-06-05arm64: dts: st: add usart6 pinctrl used on stm32mp257f-ev1 boardValentin Caron
Add pins for USART6 on GPIO connector on stm32mp257f-ev1 board. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-06-05arm64: dts: st: add usart nodes on stm32mp25Valentin Caron
Update device-tree stm32mp251.dtsi to add some USART features. Add u(s)art 1, 3, 4, 5, 6, 7, 8, 9 nodes and compatible, interrupts, clocks, access-controllers properties. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-06-05arm64: dts: st: enable STM32 access controller for RCCGabriel Fernandez
Use an STM32 access controller to filter the registration of clocks. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-06-05arm64: dts: st: OP-TEE async notif on PPI 15 for stm32mp25Etienne Carriere
Define GIC PPI 15 (aka GIC interrupt line 31) for OP-TEE asynchronous notification. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Pascal Paillet <p.paillet@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-05-14Merge tag 'irq-core-2024-05-12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull interrupt subsystem updates from Thomas Gleixner: "Core code: - Interrupt storm detection for the lockup watchdog: Lockups which are caused by interrupt storms are not easy to debug because there is no information about the events which make the lockup detector trigger. To make this more user friendly, provide an extenstion to interrupt statistics which allows to take snapshots and an interface to retrieve the delta to the snapshot. Use this new mechanism in the watchdog code to do a two stage lockup analysis by taking the snapshot and printing the deltas for the topmost active interrupts on the second trigger. Note: This contains both the interrupt and the watchdog changes as the latter depend on the former obviously. - Avoid summation loops in the /proc/interrupts output and use the global counter when possible - Skip suspended interrupts on CPU hotplug operations to ensure that they are not delivered before the system resumes the device drivers when coming out of suspend. - On CPU hot-unplug interrupts which are affine to the outgoing CPU are migrated to a different CPU in the affinity mask. This can fail when the CPUs have no vectors left. Instead of giving up try to migrate it to any online CPU and thereby breaking the affinity setting in order to prevent a stale device interrupt which targets an offline CPU - The usual small cleanups Driver code: - Support for the RISCV AIA MSI controller - Make the interrupt allocation for the Loongson PCH controller more flexible to prevent vector exhaustion - The usual set of cleanups and fixes all over the place" * tag 'irq-core-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (51 commits) irqchip/gic-v3-its: Remove BUG_ON in its_vpe_irq_domain_alloc cpuidle: Avoid explicit cpumask allocation on stack irqchip/sifive-plic: Avoid explicit cpumask allocation on stack irqchip/riscv-aplic-direct: Avoid explicit cpumask allocation on stack irqchip/loongson-eiointc: Avoid explicit cpumask allocation on stack irqchip/gic-v3-its: Avoid explicit cpumask allocation on stack irqchip/irq-bcm6345-l1: Avoid explicit cpumask allocation on stack cpumask: Introduce cpumask_first_and_and() irqchip/irq-brcmstb-l2: Avoid saving mask on shutdown genirq: Reuse irq_is_nmi() genirq/cpuhotplug: Retry with cpu_online_mask when migration fails genirq/cpuhotplug: Skip suspended interrupts when restoring affinity arm64: dts: st: Add interrupt parent to pinctrl on stm32mp251 arm64: dts: st: Add exti1 and exti2 nodes on stm32mp251 ARM: dts: stm32: List exti parent interrupts on stm32mp131 ARM: dts: stm32: List exti parent interrupts on stm32mp151 arm64: Kconfig.platforms: Enable STM32_EXTI for ARCH_STM32 irqchip/stm32-exti: Mark events reserved with RIF configuration check irqchip/stm32-exti: Skip secure events irqchip/stm32-exti: Convert driver to standard PM ...
2024-04-25arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25Patrick Delaunay
Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs. STM32MP251 is a single core Cortex A35, STM32MP253 is a dual core CA35. Fixes: 5d30d03aaf78 ("arm64: dts: st: introduce stm32mp25 SoCs family") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-04-25arm64: dts: st: add spi3 / spi8 properties on stm32mp257f-ev1Alain Volmat
Add properties for spi3 and spi8 available on the stm32mp257f-ev1. Both are kept disabled since only used via the gpio expansion connector. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-03 22:34:00 +0000