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2025-07-05ARM: dts: microchip: sama7g5: Add cache configuration for cpu nodeMihai Sain
Describe the cache memories according with datasheet chapter 15.2: - L1 cache configuration with 32KB for both data and instruction cache. - L2 cache configuration with 256KB unified cache. Before this patch the kernel reported the warning: [ 0.171425] cacheinfo: Unable to detect cache hierarchy for CPU 0 Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250619070636.8844-3-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-07-05ARM: dts: microchip: sama7d65: Add cache configuration for cpu nodeMihai Sain
Describe the cache memories according with datasheet chapter 15.2: - L1 cache configuration with 32KB for both data and instruction cache. - L2 cache configuration with 256KB unified cache. Before this patch the kernel reported the warning: [ 0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0 Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250619070636.8844-2-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-07-05ARM: dts: microchip: sama5d4: Update the cache configuration for CPUMihai Sain
Add the memory size properties for L1 and L2 according with block diagram from datasheet: - L1 cache configuration with 32 KB for both data and instruction cache. - L2 cache configuration with 128 KB unified cache. [root@sama5d4 ~]$ lscpu Architecture: armv7l Byte Order: Little Endian CPU(s): 1 On-line CPU(s) list: 0 Vendor ID: ARM Model name: Cortex-A5 Caches (sum of all): L1d: 32 KiB (1 instance) L1i: 32 KiB (1 instance) L2: 128 KiB (1 instance) Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250625064934.4828-4-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-07-05ARM: dts: microchip: sama5d3: Update the cache configuration for CPUMihai Sain
Add the memory size properties for L1 according with block diagram from datasheet: - L1 cache configuration with 32 KB for both data and instruction cache. [root@sama5d3 ~]$ lscpu Architecture: armv7l Byte Order: Little Endian CPU(s): 1 On-line CPU(s) list: 0 Vendor ID: ARM Model name: Cortex-A5 Caches (sum of all): L1d: 32 KiB (1 instance) L1i: 32 KiB (1 instance) Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250625064934.4828-3-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-07-05ARM: dts: microchip: sama5d2: Update the cache configuration for CPUMihai Sain
Add the memory size properties for L1 and L2 according with block diagram from datasheet: - L1 cache configuration with 32 KB for both data and instruction cache. - L2 cache configuration with 128 KB unified cache. [root@sama5d2 ~]$ lscpu Architecture: armv7l Byte Order: Little Endian CPU(s): 1 On-line CPU(s) list: 0 Vendor ID: ARM Model name: Cortex-A5 Caches (sum of all): L1d: 32 KiB (1 instance) L1i: 32 KiB (1 instance) L2: 128 KiB (1 instance) Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250625064934.4828-2-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-25ARM: dts: microchip: sam9x7: Add LVDS controllerDharma Balasubiramani
Add support for LVDS controller. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Link: https://lore.kernel.org/r/20250625-b4-sam9x7-dts-v1-1-92aaee14ed16@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-24ARM: dts: microchip: sama5d2_icp: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 46a8a137d8f6 ("ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250521054309.361894-4-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-24ARM: dts: microchip: sama5d27_wlsom1: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 417e58ea41ab ("ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250521054309.361894-3-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-24ARM: dts: microchip: sama5d27_som1: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 09ce8651229b ("ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250521054309.361894-2-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-24ARM: dts: microchip: sam9x60ek: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 2c0a1faa4da5 ("ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20250521054309.361894-1-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: at91-sama5d27_wlsom1: Improve the Wifi compatibleFabio Estevam
The at91-sama5d27_wlsom1 SoM has a WIL3000 Wifi SDIO device populated. Improve the description of the Wifi compatible string by passing the more specific "microchip,wilc3000" string. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250617140502.1042812-1-festevam@gmail.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: gardena-smart-gateway: Fix power LEDEzra Buehler
When starting up, the GARDENA smart Gateway's power LED should be flashing green. It is unclear why this has not been done earlier. The LED frequency cannot be configured in the devicetree. Luckily, the default is 1 Hz, which is what we want. Signed-off-by: Ezra Buehler <ezra.buehler@husqvarnagroup.com> Link: https://lore.kernel.org/r/20250612074737.311346-1-ezra@easyb.ch Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sam9x7: Add clock name propertyRyan Wanner
Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal. This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree. Fixes: 41af45af8bc3 ("ARM: dts: at91: sam9x7: add device tree for SoC") Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/036518968ac657b93e315bb550b822b59ae6f17c.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add clock name propertyRyan Wanner
Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal. This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree. Fixes: 261dcfad1b59 ("ARM: dts: microchip: add sama7d65 SoC DT") Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/3878ae6d0016d46f0c91bd379146d575d5d336aa.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7g5: Adjust clock xtal phandleRyan Wanner
Adjust clock xtal phandles to match the new xtal phandle formatting. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/8a9ece664958d07b1be73b4b6676a2a2ee397a94.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sam9x7: Add HLCD controllerDharma Balasubiramani
Add support for HLCD controller. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Link: https://lore.kernel.org/r/20250611-sam9x7-dts-v1-1-7f52fcb488ad@microchip.com [claudiu.beznea: keep reg the 1st property on port@0 to comply with dts coding style] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Enable CAN busRyan Wanner
Enable CAN bus for SAMA7D65 curiosity board. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/ab719861de53432bdf19593fa4eee40adf57aed9.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Clean up extra spaceRyan Wanner
Remove the extra space that causes formatting issues. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/ac1decc35e2b4f706cf6ab9378f2c88e5295dde4.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add CAN bus supportRyan Wanner
Add support for CAN bus to the SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/f80a4206c05ed5d80a9527476963a18070ca42b6.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add PWM supportRyan Wanner
Add support for PWMs to the SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/195c69a19be1ff14736db402e0f1ee64438b4b20.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add crypto supportRyan Wanner
Add and enable SHA, AES, TDES, and TRNG for SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/fc791949c97f368f32a710e64d8db4018e45e70f.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: use recent scl/sda gpio bindingsWolfram Sang
We have dedictaded bindings for scl/sda nowadays. Switch away from the deprecated plain 'gpios' property. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250519112107.2980-4-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-05-16ARM: dts: microchip: sama7g54_curiosity: Add fixed-partitions for spi-nor flashMihai Sain
Add fixed-partitions for spi-nor flash to match the at91 boot flow and layout of the nand flash. Partitions can be listed from /proc/mtd: [root@sama7g54 ~]$ cat /proc/mtd | grep qspi mtd6: 00040000 00001000 "qspi1: at91bootstrap" mtd7: 00100000 00001000 "qspi1: u-boot" mtd8: 00040000 00001000 "qspi1: u-boot env" mtd9: 00080000 00001000 "qspi1: device tree" mtd10: 00600000 00001000 "qspi1: kernel" [root@sama7g54 ~]$ mtdinfo /dev/mtd10 mtd10 Name: qspi1: kernel Type: nor Eraseblock size: 4096 bytes, 4.0 KiB Amount of eraseblocks: 1536 (6291456 bytes, 6.0 MiB) Minimum input/output unit size: 1 byte Sub-page size: 1 byte Character device major/minor: 90:20 Bad blocks are allowed: false Device is writable: true Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250429064547.5807-1-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-05-16ARM: dts: microchip: sama7d65: Add RTT timer to curiosity boardRyan Wanner
Add RTT timer with backup register for SAMA7D65_Curiosity board. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/463581224a07bf122c6907d34a0c5c71b1cc73e1.1744666011.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-05-16ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoCRyan Wanner
Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able to store the RTT time data. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/e8868ef06102241b47883ba10edaed751831be6d.1744666011.git.Ryan.Wanner@microchip.com [claudiu.beznea: keep nodes sorted by their address] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-05-16ARM: dts: microchip: sama7d65: Add SRAM and DRAM components supportRyan Wanner
Add SRAM, secumod, UDDRC, and DDR3phy to enable support for low power modes. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/354ecd628fdd292d2125570a6b10a93cbecb7706.1744666011.git.Ryan.Wanner@microchip.com [claudiu.beznea: keep nodes sorted by their address] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-05-16ARM: dts: microchip: sama7d65_curiosity: add EEPROMRyan Wanner
If the MAC address is not fetched and loaded by U-boot then Linux will have to load the address. The EEPROM and nvmem-layout to describe EUI48 MAC address regions. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/96ee6832d9b55acfae8d3560f625798025dfd89c.1743523114.git.Ryan.Wanner@microchip.com [claudiu.beznea: added nvmem properties in gmac0 node before the status one] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-05-16ARM: dts: microchip: sama7d65: Add MCP16502 to sama7d65 curiosityRyan Wanner
Add MCP16502 to the sama7d65_curiosity board to control voltages in the MPU. The device is connected to twi 10 interface Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/60f6b7764227bb42c74404e8ca1388477183b7b5.1743523114.git.Ryan.Wanner@microchip.com [claudiu.beznea: drop regulator-suspend-voltage for ldo2 as it is not needed] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-05-16ARM: dts: microchip: sama7d65: Enable GMAC interfaceRyan Wanner
Enable GMAC0 interface for sama7d65_curiosity board. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/fca0c1deb74006cdedbdd71061dec9dabf1e9b9a.1743523114.git.Ryan.Wanner@microchip.com [claudiu.beznea: move gmac0 node to keep the nodes alphanumerically sorted, dropped status property on the PHY node, added missing blank line] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-05-16ARM: dts: microchip: sama7d65: Add FLEXCOMs to sama7d65 SoCRyan Wanner
Add FLEXCOMs to the SAMA7D65 SoC device tree. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/d474fcd850978261ac889950ac1c3a36bc6d3926.1743523114.git.Ryan.Wanner@microchip.com [claudiu.beznea: use vendor specific properties at the end of the node, align DMA entries, add missing spaces] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-05-16ARM: dts: microchip: sama7d65: Add gmac interfaces for sama7d65 SoCRyan Wanner
Add support for GMAC interfaces on SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/05b107796b6f3a173d0dd0a5b2107b675cfd994e.1743523114.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: at91sam9263: fix NAND chip selectsWolfram Sang
NAND did not work on my USB-A9263. I discovered that the offending commit converted the PIO bank for chip selects wrongly, so all A9263 boards need to be fixed. Fixes: 1004a2977bdc ("ARM: dts: at91: Switch to the new NAND bindings") Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20250402210446.5972-2-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: usb_a9g20: move wrong RTC nodeWolfram Sang
Only the LPW variant has the external RTC. Move it to that board specific DT. As a result, the common include for A9G20 boards can go now. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20250402204856.5197-5-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: calao_usb: simplify chosen nodeWolfram Sang
All devices use equal parameters in 'chosen'. So, the memory node can be put into the most generic DTSI. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20250402204856.5197-4-wsa+renesas@sang-engineering.com [claudiu.beznea: s/can bet put/can be put/g in commit description] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: usb_a9260: use 'stdout-path'Wolfram Sang
Do not use the kernel command line for specifying the default serial console. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20250402204856.5197-3-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: calao_usb: simplify memory nodeWolfram Sang
All devices have 64MB RAM. So, the memory node can be put into the most generic DTSI. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20250402204856.5197-2-wsa+renesas@sang-engineering.com [claudiu.beznea: s/can bet put/can be put/g in commit description] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: usb_a9263: fix GPIO for Dataflash chip selectWolfram Sang
Dataflash did not work on my board. After checking schematics and using the proper GPIO, it works now. Also, make it active low to avoid: flash@0 enforce active low on GPIO handle Fixes: 2432d201468d ("ARM: at91: dt: usb-a9263: add dataflash support") Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20250404112742.67416-2-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: usb_a9g20: add SPI EEPROMWolfram Sang
Schematics and board layout indicate that versions with a dataflash instead of an EEPROM might exist. Let's handle that once we have hardware to test. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20250403064336.4846-2-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-03-04ARM: dts: microchip: sama7g5: add ADC hw trigger edge typeNayab Sayed
Set ADC trigger edge type property as interrupt edge rising value. Signed-off-by: Nayab Sayed <nayabbasha.sayed@microchip.com> Link: https://lore.kernel.org/r/20250304-sama7g5-hw-trigger-enable-v1-1-61b5618285f0@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-03-03ARM: dts: microchip: sama7d65: Add watchdog for sama7d65Ryan Wanner
Add watchdog timer support for SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/05785a34b9181b7debb57c1896cc733bd3088c56.1740675317.git.Ryan.Wanner@microchip.com [claudiu.beznea: fixed conflict] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-03-02ARM: dts: microchip: sama7d65: Enable shutdown controllerRyan Wanner
Enable shutdown controller to support shutdown and wake up. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/c31c40eb388b2fc0ad6ee17ed2e23bcd04e8e1c8.1740671156.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-03-02ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65Ryan Wanner
Add SFRBU support to the SAMA7D65 SoC. This is required to change the power source for backup mode for the SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/dbc51f95f301c106c031fb93f84d0d847e818d91.1740671156.git.Ryan.Wanner@microchip.com [claudiu.beznea: fixed conflict] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-03-02ARM: dts: microchip: sama7d65: Add RTC support for sama7d65Ryan Wanner
Add RTC support for the SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/fa1587ffef21a8198317062c15d8eb5c3ca6187c.1740671156.git.Ryan.Wanner@microchip.com [claudiu.beznea: fixed conflict, keep nodes sorted by their addresses] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-03-02ARM: dts: microchip: sama7d65: Add Shutdown controller supportRyan Wanner
Add shutdown controller support for SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/ffc76b757cd1ba4ca38947f8b30525b848aa8ad7.1740671156.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-03-02ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoCRyan Wanner
Add Reset Controller support to SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/a9620ff11456a1ddfb9c289421606602193ce5b6.1740671156.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-02-28ARM: dts: microchip: fix faulty ohci/ehci node namesWolfram Sang
They should be named "usb@". Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20250226084938.3436-10-wsa+renesas@sang-engineering.com [claudiu.beznea: replace at91 w/ microchip in commit title] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-02-28ARM: dts: microchip: usb_a9263: fix wrong vendorWolfram Sang
The board was made by Calao, not by Atmel. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20250226084938.3436-9-wsa+renesas@sang-engineering.com [claudiu.beznea: replaced at91 w/ microchip in commit title] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-02-24ARM: dts: microchip: sama7d65: Enable DMAsRyan Wanner
Enable DMA interface for sama7d65_curiosity board. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/e233ab028123bd91b1de7b0f02eb966d719cc0af.1739555984.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-02-24ARM: dts: microchip: sama7d65: Add DMAs to sama7d65 SoCRyan Wanner
Add DMAs to the SAMA7D65 SoC device tree. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/78da4125a991c6f4081fce78825f1f983091e0f5.1739555984.git.Ryan.Wanner@microchip.com [claudiu.beznea: dropped extra space in reg property of dma0] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-02-24ARM: dts: microchip: sama7d65: Add chipID for sama7d65Ryan Wanner
Add chipID for the sama7d65 SoC to the device tree. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/14e6cafb64df345e6bd79ac96961248cc266770c.1739555984.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-30 11:10:05 +0000