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2024-02-06dt-bindings: firmware: xilinx: Describe soc-nvmem subnodeMichal Simek
Describe soc-nvmem subnode as the part of firmware node. The name can't be pure nvmem because dt-schema already defines it as array property that's why different name should be used. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/24fe6adbf2424360618e8f5ca541ebfd8bb0723e.1706692641.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-22dt-bindings: firmware: xilinx: Sort node names (clock-controller)Michal Simek
Nodes should be sorted that's why move clock-controller to the top of list. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/ccb6bd5f4d1d28983c73497ada596e893fece499.1703161663.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-22dt-bindings: firmware: xilinx: Describe missing child nodesMichal Simek
Firmware node has more than fpga, aes and clock child nodes but also power, reset, gpio, pinctrl and pcap which are not described yet. All of them have binding in separate files but there is missing connection to firmware node that's why describe it. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1d7988cfadf3554d11f0779f96a670b4fd86ce5a.1703161663.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-22dt-bindings: firmware: xilinx: Fix versal-fpga node nameMichal Simek
Based on commit 83a368a3fc8a ("docs: dt-bindings: add DTS Coding Style document") using underscore ('_') in node name is not recommended that's why switch to dash ('-'). Acked-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/6779af2f9cc21c912f10cf310388d99b980800b2.1702996281.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-01-22dt-bindings: firmware: versal: add versal-net compatible stringJay Buddhabhatti
Add dt-binding documentation for Versal NET platforms. Versal Net is a new AMD/Xilinx SoC. The SoC and its architecture is based on the Versal ACAP device. The Versal Net device includes more security features in the platform management controller (PMC) and increases the number of CPUs in the application processing unit (APU) and the real-time processing unit (RPU). Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1705406326-2947516-1-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-17dt-bindings: Remove alt_ref from versalShubhrajyoti Datta
The alt_ref is present only in Versal-net devices. Other versal devices do not have it. So remove alt_ref for versal. Fixes: 352546805a44 ("dt-bindings: clock: Add bindings for versal clock driver") Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Link: https://lore.kernel.org/r/20231128104348.16372-1-shubhrajyoti.datta@amd.com Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-18dt-bindings: power: xilinx: merge zynqmp-genpd.txt with firmware bindingNaman Trivedi Manojbhai
Remove the zynqmp-genpd.txt binding. Add the power-domain-cells property from the zynqmp-genpd.txt binding to firmware binding. Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230816130309.1338446-1-naman.trivedimanojbhai@amd.com Signed-off-by: Rob Herring <robh@kernel.org>
2023-06-05dt-bindings: xilinx: Switch xilinx.com emails to amd.comMichal Simek
@xilinx.com is still working but better to switch to new amd.com after AMD/Xilinx acquisition. Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Acked-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com
2021-07-21dt-bindings: firmware: Remove xlnx,zynqmp-firmware.txt fileNava kishore Manne
The funtionality of xlnx,zynqmp-firmware.txt is replaced with xlnx,zynqmp-firmware.yaml bindings so this patch removes the zynqmp-firmware.txt file Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Link: https://lore.kernel.org/r/20210626155248.5004-5-nava.manne@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-07-21dt-bindings: firmware: Add bindings for xilinx firmwareNava kishore Manne
Add documentation to describe Xilinx firmware driver bindings. Firmware driver provides an interface to firmware APIs. Interface APIs can be used by any driver to communicate to Platform Management Unit. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Link: https://lore.kernel.org/r/20210626155248.5004-4-nava.manne@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-10-16dt-bindings: firmware: Add bindings for Versal firmwareJolly Shah
ZynqMP firmware driver can be used for versal also. Add versal compatible string to zynqmp firmware driver doc. Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-03-18dt-bindings: xilinx: Separate clock binding from firmware docRajan Vaja
Clock description is part of firmware doc. Move clock description in separate doc. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-03-18include: dt-binding: clock: Rename zynqmp header fileJolly Shah
Rename file name of ZynqMP clk dt-bindings to align with file name of reset and power dt-bindings. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-09dt-bindings: clock: Add bindings for ZynqMP clock driverRajan Vaja
Add documentation to describe Xilinx ZynqMP clock driver bindings. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26dt-bindings: firmware: Add bindings for ZynqMP firmwareRajan Vaja
Add documentation to describe Xilinx ZynqMP firmware driver bindings. Firmware driver provides an interface to firmware APIs. Interface APIs can be used by any driver to communicate to PMUFW (Platform Management Unit). Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>