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2023-12-15arm64: dts: qcom: sm6115: switch UFS QMP PHY to new style of bindingsDmitry Baryshkov
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231205032552.1583336-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: sdm845: switch UFS QMP PHY to new style of bindingsDmitry Baryshkov
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231205032552.1583336-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: msm8998: switch UFS QMP PHY to new style of bindingsDmitry Baryshkov
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231205032552.1583336-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: msm8996: switch UFS QMP PHY to new style of bindingsDmitry Baryshkov
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231205032552.1583336-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: sm8450-hdk: Enable the A730 GPUKonrad Dybcio
Enable the GPU and provide a path for the ZAP blob. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231127-topic-a7xx_dt-v2-6-2a437588e563@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: sm8550-mtp: Enable the A740 GPUKonrad Dybcio
Enable the GPU and provide a path for the ZAP blob. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231127-topic-a7xx_dt-v2-5-2a437588e563@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: sm8550-qrd: Enable the A740 GPUKonrad Dybcio
Enable the GPU and provide a path for the ZAP blob. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Link: https://lore.kernel.org/r/20231127-topic-a7xx_dt-v2-4-2a437588e563@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: sm8550: Add GPU nodesKonrad Dybcio
Add the required nodes to support the A740 GPU. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Link: https://lore.kernel.org/r/20231127-topic-a7xx_dt-v2-3-2a437588e563@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: sm8450: Add GPU nodesKonrad Dybcio
Add the required nodes to support the A730 GPU. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231127-topic-a7xx_dt-v2-2-2a437588e563@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: msm8939: Make blsp_dma controlled-remotelyStephan Gerhold
The blsp_dma controller is shared between the different subsystems, which is why it is already initialized by the firmware. We should not reinitialize it from Linux to avoid potential other users of the DMA engine to misbehave. In mainline this can be described using the "qcom,controlled-remotely" property. In the downstream/vendor kernel from Qualcomm there is an opposite "qcom,managed-locally" property. This property is *not* set for the qcom,sps-dma@7884000 [1] so adding "qcom,controlled-remotely" upstream matches the behavior of the downstream/vendor kernel. Adding this seems to fix some weird issues with UART where both input/output becomes garbled with certain obscure firmware versions on some devices. [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.2.9.1-02310-8x16.0/arch/arm/boot/dts/qcom/msm8939-common.dtsi#L866-872 Cc: stable@vger.kernel.org # 6.5 Fixes: 61550c6c156c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231204-msm8916-blsp-dma-remote-v1-2-3e49c8838c8d@gerhold.net Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: msm8916: Make blsp_dma controlled-remotelyStephan Gerhold
The blsp_dma controller is shared between the different subsystems, which is why it is already initialized by the firmware. We should not reinitialize it from Linux to avoid potential other users of the DMA engine to misbehave. In mainline this can be described using the "qcom,controlled-remotely" property. In the downstream/vendor kernel from Qualcomm there is an opposite "qcom,managed-locally" property. This property is *not* set for the qcom,sps-dma@7884000 [1] so adding "qcom,controlled-remotely" upstream matches the behavior of the downstream/vendor kernel. Adding this seems to fix some weird issues with UART where both input/output becomes garbled with certain obscure firmware versions on some devices. [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.2.9.1-02310-8x16.0/arch/arm/boot/dts/qcom/msm8916.dtsi#L1466-1472 Cc: stable@vger.kernel.org # 6.5 Fixes: a0e5fb103150 ("arm64: dts: qcom: Add msm8916 BLSP device nodes") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231204-msm8916-blsp-dma-remote-v1-1-3e49c8838c8d@gerhold.net Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: msm8939: Add clock-frequency for broadcast timerStephan Gerhold
Looks like not all firmware versions used for MSM8939 program the timer frequency for both broadcast/MMIO timers, causing a WARNING at runtime: WARNING: CPU: 0 PID: 0 at kernel/time/clockevents.c:38 cev_delta2ns+0x74/0x90 pc : cev_delta2ns+0x74/0x90 lr : clockevents_config.part.0+0x64/0x8c Call trace: cev_delta2ns+0x74/0x90 clockevents_config_and_register+0x20/0x34 arch_timer_mem_of_init+0x374/0x534 timer_probe+0x88/0x110 time_init+0x14/0x4c start_kernel+0x2c0/0x640 Unfortunately there is no way to fix the firmware on most of these devices since it's proprietary and signed. As a workaround, specify the clock-frequency explicitly in the DT to fix the warning. Fixes: 61550c6c156c ("arm64: dts: qcom: Add msm8939 SoC") Reported-by: Vincent Knecht <vincent.knecht@mailoo.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231204-msm8939-timer-v1-1-a2486c625786@gerhold.net Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: Add missing vio-supply for AW2013Stephan Gerhold
Add the missing vio-supply to all usages of the AW2013 LED controller to ensure that the regulator needed for pull-up of the interrupt and I2C lines is really turned on. While this seems to have worked fine so far some of these regulators are not guaranteed to be always-on. For example, pm8916_l6 is typically turned off together with the display if there aren't any other devices (e.g. sensors) keeping it always-on. Cc: stable@vger.kernel.org # 6.6 Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20231204-qcom-aw2013-vio-v1-1-5d264bb5c0b2@gerhold.net Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: ipq6018: Add QUP5 SPI nodeChukun Pan
Add node to support the QUP5 SPI controller inside of IPQ6018. Some routers use this bus to connect SPI TPM chips. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20231203154003.532765-1-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: ipq6018: Add remaining QUP UART nodeChukun Pan
Add node to support all the QUP UART node controller inside of IPQ6018. Some routers use these bus to connect Bluetooth chips. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15arm64: dts: qcom: qrb4210-rb2: Enable MPSS and Wi-FiKonrad Dybcio
Enable the remote processors and tighten up the regulators to enable Wi-Fi functionality on the RB2. For reference, the hw/sw identifies as: qmi chip_id 0x150 chip_family 0x4002 board_id 0xff soc_id 0x40670000 qmi fw_version 0x337302d3 fw_build_timestamp 2023-01-06 01:50 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.3.7.c2-00723-QCAHLSWMTPLZ-1 wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 htt-ver 3.114 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231104-topic-rb2_wifi-v1-1-fd45ae535d2f@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-16arm64: dts: freescale: fix the schema check errors for fsl,tmu-calibrationDavid Heidelberg
fsl,tmu-calibration contains cell pairs (u32-matrix). Mark them as such. Use matching property syntax and allow correct validation. No functional changes. Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-16ARM: dts: imx27-phytec-phycore-som: Use 'rtc' as node nameFabio Estevam
Node names should be generic. Use 'rtc' for the rtc node to fix the following dt-schema warning: imx27-phytec-phycore-rdk.dtb: pcf8563@51: $nodename:0: 'pcf8563@51' does not match '^rtc(@.*|-([0-9]|[1-9][0-9]+))?$' from schema $id: http://devicetree.org/schemas/rtc/nxp,pcf8563.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-16ARM: dts: imx25: Remove unneeded keypad propertiesFabio Estevam
Per imx-keypad.yaml, '#address-cells', '#size-cells', 'clock-names' are not valid properties. Remove them to fix the following dt-schema warning: imx25-pdk.dtb: kpp@43fa8000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'clock-names' were unexpected) from schema $id: http://devicetree.org/schemas/input/imx-keypad.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-16arm64: dts: freescale: imx8qxp: Disable dsp reserved memory by defaultAlexander Stein
Even if the 'dsp' node is disabled the memory intended to be used by the DSP is reserved. This limits the memory range suitable for CMA allocation. Thus disable the dsp_reserved node. DSP users need to enable it in parallel to the 'dsp' node. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-16arm64: dts: imx8qxp: Add VPU subsystem fileAlexander Stein
imx8qxp re-uses imx8qm VPU subsystem file, but it has different base addresses. Also imx8qxp has only two VPU cores, delete vpu_vore2 and mu2_m0 accordingly. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-16arm64: dts: imx8qxp-mek: Move port under USB connectorFabio Estevam
Per nxp,ptn5110.yaml, 'port' should be placed under 'connector'. Do as requested to fix the following dt-schema warning: imx8qxp-mek.dtb: tcpc@50: connector:ports: 'port@0' is a required property from schema $id: http://devicetree.org/schemas/usb/nxp,ptn5110.yaml# imx8qxp-mek.dtb: tcpc@50: connector: Unevaluated properties are not allowed ('ports' was unexpected) from schema $id: http://devicetree.org/schemas/usb/nxp,ptn5110.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-16arm64: dts: imx8mn-bsh-smm-s2/pro: add display setupMichael Trimarchi
Add the display and nodes required for its operation. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-15ARM: dts: ux500-href: Switch HREF520 to AB8505Linus Walleij
After noticing a tendency to misbehave and randomly power down: switch the HREF520 AB8500 to the AB8505, which is what it has mounted. After this the board works better. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231214-ux500-no-turnoff-lowbatt-v1-3-9dcff0783d62@linaro.org
2023-12-15ARM: dts: ux500-href: Push AB8500 config outLinus Walleij
Push out some AB8500 setup of regulators and phy out to the per-AB850x variant file ste-href-ab8500.dtsi so it becomes self-contained for each AB850x chip. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231214-ux500-no-turnoff-lowbatt-v1-2-9dcff0783d62@linaro.org
2023-12-15ARM: dts: ux500-href: Push AB8500 inclusion to the topLinus Walleij
On the hardware reference designs, include the AB8500 definitions on the top level in the DTS files, this is to make it possible to use the AB8505 in the HREF520. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231214-ux500-no-turnoff-lowbatt-v1-1-9dcff0783d62@linaro.org
2023-12-15arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed modeBhavya Kapoor
DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD High Speed DDR which is DDR50 speed mode for J784s4 SoC according to datasheet for J784s4. [+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J784s4 datasheet - https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Judith Mendez <jm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231201082045.790478-4-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed modeBhavya Kapoor
DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD High Speed DDR which is DDR50 speed mode for J721s2 SoC according to datasheet for J721s2. [+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J721s2 datasheet - https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Judith Mendez <jm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231201082045.790478-3-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed modeBhavya Kapoor
DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for eMMC High Speed DDR which is DDR52 speed mode for J7200 SoC according to datasheet for J7200. [+] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface, in J7200 datasheet - https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Judith Mendez <jm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231201082045.790478-2-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: ti: k3-am6*: Add additional regs for DMA componentsVignesh Raghavendra
Add additional reg properties for BCDMA and PKTDMA nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231213135138.929517-4-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: ti: k3-j7*: Add additional regs for DMA componentsManorit Chawdhry
Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231213135138.929517-3-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: ti: k3-am65: Add additional regs for DMA componentsManorit Chawdhry
Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-15arm64: dts: cn913x: add device trees for COM Express boardsElad Nachman
Add support for CN9130 and CN9131 COM Express Type 7 CPU module boards by Marvell. Define these COM Express CPU modules as dtsi and provide a dtsi file for a carrier board (Marvell AC5X RD COM Express type 7 carrier board). This Carrier board only utilizes the PCIe link, hence no special device / driver support is provided by this dtsi file. Finally, provide a dts file for the com express carrier and CPU module combination. These COM Express boards differ from the existing CN913x DB boards by the type of ethernet connection (RGMII), the type of voltage regulators (not i2c expander based) and the USB phy (not UTMI based). Note - PHY + RGMII connector is OOB on CPU module. CN9131 COM Express board is basically CN9130 COM Express board with an additional CP115 I/O co-processor, which in this case provides an additional USB host controller on the board. Signed-off-by: Elad Nachman <enachman@marvell.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-12-15dt-bindings: arm64: add Marvell COM Express boardsElad Nachman
Add dt bindings for: CN9130 COM Express CPU module CN9131 COM Express CPU module AC5X RD COM Express Type 7 carrier board. AC5X RD COM Express board with a CN9131 COM Express Type 7 CPU module. Signed-off-by: Elad Nachman <enachman@marvell.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-12-15MAINTAINERS: add ac5 to list of maintained Marvell dts filesElad Nachman
Add ac5 dts files to the list of maintained Marvell Armada dts files by defining the entry as covering the entire marvell arm64 directory Signed-off-by: Elad Nachman <enachman@marvell.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-12-15arm64: dts: armada-3720-turris-mox: set irq type for RTCSjoerd Simons
The rtc on the mox shares its interrupt line with the moxtet bus. Set the interrupt type to be consistent between both devices. This ensures correct setup of the interrupt line regardless of probing order. Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Cc: <stable@vger.kernel.org> # v6.2+ Fixes: 21aad8ba615e ("arm64: dts: armada-3720-turris-mox: Add missing interrupt for RTC") Reviewed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-12-15ARM64: dts: Add special compatibles for the Turris MoxLinus Walleij
These special compatibles are added to the Marvell Armada 3720 Turris Mox in order to be able to special-case and avoid warnings on the non-standard nodenames that are ABI on this one board due to being used in deployed versions of U-Boot. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-12-15ARM64: dts: marvell: Fix some common switch mistakesLinus Walleij
Fix some errors in the Marvell MV88E6xxx switch descriptions: - The top node had no address size or cells. - switch0@0 is not OK, should be ethernet-switch@0. - ports should be ethernet-ports - port@0 should be ethernet-port@0 - PHYs should be named ethernet-phy@ Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-12-15ARM: dts: marvell: make dts use gpio-fan matrix instead of arrayDavid Heidelberg
No functional changes. Adjust to comply with dt-schema requirements and make possible to validate values. Acked-by: Simon Guinot <simon.guinot@sequanux.org> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-12-15ARM: dts: marvell: Fix some common switch mistakesLinus Walleij
Fix some errors in the Marvell MV88E6xxx switch descriptions: - The top node had no address size or cells. - switch0@0 is not OK, should be ethernet-switch@0. - The ports node should be named ethernet-ports - The ethernet-ports node should have port@0 etc children, no plural "ports" in the children. - Ports should be named ethernet-port@0 etc - PHYs should be named ethernet-phy@0 etc This serves as an example of fixes needed for introducing a schema for the bindings, but the patch can simply be applied. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2023-12-15ARM: dts: stm32: add dcmipp support to stm32mp135Hugues Fruchet
Add dcmipp support to STM32MP135. Signed-off-by: Hugues Fruchet <hugues.fruchet@foss.st.com> Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2023-12-14arm64: dts: allwinner: h618: add Transpeed 8K618-T TV boxAndre Przywara
This is a Chinese TV box, probably very similar if not identical to various other cheap TV boxes with the same specs: - Allwinner H618 SoC (4 * Arm Cortex-A53 cores, 1MB L2 cache) - 2 or 4GiB DDR3L DRAM - 32, 64, or 128 GiB eMMC flash - AXP313a PMIC - 100 Mbit/s Ethernet (using yet unsupported internal PHY) - HDMI port - 2 * USB 2.0 ports - microSD card slot - 3.5mm A/V port - 7-segment display - 5V barrel plug power supply The PCB provides holes for soldering a UART header or cable, this is connected to the debug UART0. UART1 is used for the Bluetooth chip, although this isn't working yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20231214015312.17363-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-12-14dt-bindings: arm: sunxi: document Transpeed 8K618-T board nameAndre Przywara
The Transpeed 8K618-T TV box is a Chinese Android TV box, using the Allwinner H618 SoC. Add the board/SoC compatible string pair to the list of known boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231214015312.17363-3-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-12-14dt-bindings: vendor-prefixes: add TranspeedAndre Przywara
This is a name used by some Chinese TV boxes, add it to the bindings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231214015312.17363-2-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-12-14arm64: dts: st: add bsec support to stm32mp25Patrick Delaunay
Add BSEC support to STM32MP25 SoC family with SoC information: - RPN = Device part number (BSEC_OTP_DATA9) - PKG = package data register (Bits 2:0 of BSEC_OTP_DATA122) Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2023-12-14ARM: dts: stm32: Consolidate usbh_[eo]hci phy properties on stm32mp15Uwe Kleine-König
All machines making use of &usbh_ehci and/or &usbh_ohci use phys = <&usbphyc_port0>; So move this setting into the .dtsi. Also add phy-names = "usb"; which isn't used by all machines, but nice for consistency. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2023-12-14ARM: dts: stm32: don't mix SCMI and non-SCMI board compatiblesAhmad Fatoum
The binding erroneously decreed that the SCMI variants of the ST evaluation kits are compatible with the non-SCMI variants. This is not correct, as a kernel or bootloader compatible with the non-SCMI variant is not necessarily able to function, when direct access to resources is replaced by having to talk SCMI to the secure monitor. The binding has been adjusted to reflect thus, so synchronize the device trees now. Fixes: 5b7e58313a77 ("ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2023-12-14dt-bindings: arm: stm32: don't mix SCMI and non-SCMI board compatiblesAhmad Fatoum
SCMI-enabled boards may restrict access to resources like clocks, resets and regulators to the secure world. A normal world bootloader or kernel compatible with the non-SCMI-enabled board is thus not guaranteed to be able to deal with the SCMI variant. It follows, that the SCMI-enabled board is not compatible with the non-SCMI enabled board, so drop that compatible. This change is motivated by the barebox' bootloader's use of bootloader specification files[1][2]: barebox for non-SCMI DK2 will compare its own top-level "stm32mp157c-dk2" compatible with all compatibles listed in the device tree referenced by each bootloader spec file. If the boot medium contains a configuration with compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; it will match, because of the second compatible and boot a kernel with SCMI enabled, although no SCMI may exist on the platform. [1]: https://uapi-group.org/specifications/specs/boot_loader_specification/ [2]: https://www.barebox.org/doc/latest/user/booting-linux.html#boot-loader-specification Fixes: 8e14ebb1f08f ("dt-bindings: arm: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2023-12-14ARM: dts: stm32: minor whitespace cleanup around '='Krzysztof Kozlowski
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2023-12-14arm64: dts: imx8mp-dhcom-pdk3: Describe the USB-C connectorFabio Estevam
Describe the PTN5150 USB-C connector to improve the devicetree description and fix the following dt-schema warning: imx8mp-dhcom-pdk3.dtb: typec@3d: 'port' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/extcon/extcon-ptn5150.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-06 00:10:24 +0000