diff options
| author | Chukun Pan <amadeus@jmu.edu.cn> | 2023-12-03 23:40:03 +0800 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-12-15 23:04:04 -0600 |
| commit | 2e16f9dc9be07f08442d63d682cdf89d6321b408 (patch) | |
| tree | 0fd12d87f184fd240ce4b08f94082655017c52b3 | |
| parent | e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 (diff) | |
arm64: dts: qcom: ipq6018: Add QUP5 SPI node
Add node to support the QUP5 SPI controller inside of IPQ6018.
Some routers use this bus to connect SPI TPM chips.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20231203154003.532765-1-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index f7359de98d702..4fa1b4b649d58 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -534,6 +534,20 @@ status = "disabled"; }; + blsp1_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x078b9000 0x0 0x600>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + blsp1_i2c2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; |