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2022-11-18arm: dts: socfpga: align mmc node names with dtschemaDinh Nguyen
dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$' Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDESYoshihiro Shimoda
Enable Ethernet Switch and SERDES for R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20221118120953.1186392-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-18arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodesYoshihiro Shimoda
Add Ethernet Switch and SERDES nodes into R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20221118120953.1186392-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-18arm64: dts: fvp: Add information about L1 and L2 cachesSudeep Holla
Add the information about L1 and L2 caches on FVP RevC platform. Though the cache size is configurable through the model parameters, having default values in the device tree helps to exercise and debug any code utilising the cache information without the need of real hardware. Link: https://lore.kernel.org/r/20221118151017.704716-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-11-18arm64: dts: fvp: Add SPE to Foundation FVPJames Clark
Add SPE DT node to FVP model. If the model doesn't support SPE (e.g., turned off via parameter), the driver will skip the initialisation accordingly and thus is safe. Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20221117102536.237515-1-james.clark@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-11-18ARM: dts: lpc32xx: trim addresses to 8 digitsKrzysztof Kozlowski
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Link: https://lore.kernel.org/r/20221115105049.95313-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18ARM: dts: imx: trim addresses to 8 digitsKrzysztof Kozlowski
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Link: https://lore.kernel.org/r/20221115105051.95345-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18ARM: dts: omap: trim addresses to 8 digitsKrzysztof Kozlowski
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20221115105053.95430-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18ARM: tegra: Remove duplicate pin entry in pinmuxThierry Reding
For Tegra30 Pegatron Chagall, the sdmmc3_dat3_pb5 pin was defined multiple times, leading to a DT validation error. Remove the duplicate entry. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Remove unused interrupt-parent propertiesThierry Reding
Some boards are using the interrupt-parent property to point at the GPIO controller since it handles the interrupts for the GPIO keys. However, a node needs an interrupts property for interrupt-parent to be meaningful, which these boards don't have. gpio-keys in these cases will directly use the GPIO lines specified in the key definitions and rely on the implicit conversion of those GPIOs to interrupts by the operating system, so explicit specification of the interrupts is not required. Remove the unnecessary interrupt-parent properties. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Fix nvidia,io-reset propertiesThierry Reding
Rename the unknown nvidia,ioreset property to nvidia,io-reset, as specified in the DT bindings and supported by the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Add missing power-supply for panelsThierry Reding
Tegra124 Nyan and Venice 2 boards were missing the required power-supply property in their display panel device tree nodes. Add these properties to fix validation errors. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Fixup pinmux node namesThierry Reding
Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Use correct compatible string for ASUS TF101 panelThierry Reding
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-17riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2CLad Prabhakar
Enable CANFD and I2C on RZ/Five SMARC EVK. Note, these blocks are enabled in RZ/G2UL SMARC EVK DTSI [0] hence deleting these disabled nodes from RZ/Five SMARC EVK DTSI enables them here too as we include [0] in RZ/Five SMARC EVK DTSI. [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221115105135.1180490-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal ↵Lad Prabhakar
Zones/TSU Enable support for below blocks found on RZ/Five SMARC EVK SoC/SoM: - ADC - OPP - Thermal Zones - TSU Note, these blocks are enabled in RZ/G2UL SMARC SoM DTSI [0] hence deleting these disabled nodes from RZ/Five SMARC SoM DTSI enables them here too as we include [0] in RZ/Five SMARC SoM DTSI. [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221115105135.1180490-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17arm64: dts: renesas: r9a09g011: Add system controller nodeBiju Das
Add system controller node to RZ/V2M SoC dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221116102140.852889-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17arm64: dts: renesas: r8a779g0: Add CA76 operating pointsGeert Uytterhoeven
Add operating points for running the Cortex-A76 CPU cores on R-Car V4H at various speeds, up to the Normal (1.7 GHz) performance mode. Based on a patch in the BSP by Tho Vu. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8afb32f5dc123ebf2b941703483152ff0992191d.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add CPU core clocksGeert Uytterhoeven
Describe the clocks for the four Cortex-A76 CPU cores. CA76 Sub-Systems 0/1 (both clusters / all CPU cores) are clocked by Z0φ. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/aa6e9ae21e451ebd40d54d986bd0296571128d5b.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add CPUIdle supportGeert Uytterhoeven
Support CPUIdle for ARM Cortex-A76 on R-Car V4H. Based on patches in the BSP by Tho Vu and Vincent Bryce. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f6d4076983eb45cf23595a045747f28cbdcdf4e6.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU coresGeert Uytterhoeven
Complete the description of the Cortex-A76 CPU cores and L3 cache controllers on the Renesas R-Car V4H (R8A779G0) SoC, including CPU topology and PSCI support for enabling CPU cores. R-Car V4H has 4 Cortex-A76 cores, grouped in 2 clusters. Based on a patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ccb55458bd87f8ba70d28c61bcc254f22184824c.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add L3 cache controllerGeert Uytterhoeven
Describe the cache configuration for the first Cortex-A76 CPU core on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be
2022-11-17riscv: dts: microchip: remove unused pcie clocksConor Dooley
The PCIe root port in the designs that ship with the PolarBerry and M100PFSEVP are connected via one, not two Fabric Interface Controllers (FIC). The one at 0x20_0000_0000 is fic0, so remove the fic1 clocks from the dt node. The same clock provides both, so this is harmless but inaccurate. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-17riscv: dts: microchip: remove pcie node from the sev kitConor Dooley
The SEV kit reference design does not hook up the PCIe root port to the core complex including it is misleading. The entry is a re-use mistake - I was not aware of this when I moved the PCIe node out of mpfs.dtsi so that individual bistreams could connect it to different fics etc. The node is disabled, so there should be no functional change here. Fixes: 978a17d1a688 ("riscv: dts: microchip: add sevkit device tree") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-17dt-bindings: arm: renesas: Document Renesas RZ/V2M System ConfigurationPhil Edworthy
Add DT binding documentation for System Configuration (SYS) found on RZ/V2M SoC's. SYS block contains the SYS_VERSION register which can be used to retrieve SoC version information. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221116102140.852889-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17arm64: dts: mediatek: mt7986: Add SoC compatibleMatthias Brugger
Missing SoC compatible in the board file causes dt bindings check. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Link: https://lore.kernel.org/r/20221114121653.14739-1-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-17ARM: dts: at91: sama7g5: fix signal name of pin PD8Mihai Sain
The signal name of pin PD8 with function D is A22_NANDCLE as it is defined in the datasheet. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> [claudiu.beznea: rebased on top of 6.1-rc1, removed fixes tag] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221114151035.2926-1-mihai.sain@microchip.com
2022-11-17ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench boardMarek Vasut
Replace "mdio0" node with "mdio" to match mdio.yaml DT schema. Fixes: c8ce0dd75515b ("ARM: dts: stm32: Add DHCOR based Testbench board") Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-17ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dkAmelie Delaunay
MCP23017 is an IO expander offering 16 input/output port expander with interrupt output. On stm32mp135f-dk, only INTA is routed (on PG12), but MCP23017 can mirror the bank B interrupts on INTA, that's why the property microchip,irq-mirror is used. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-17ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13Amelie Delaunay
MCP23017 interrupt line (routed on PG12) requires to be pulled-up. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-16arm64: dts: ti: k3-j721s2-main: Enable crypto acceleratorJayesh Choudhary
Add the node for SA2UL for supporting hardware crypto algorithms, including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites. Add rng node for hardware random number generator. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com> Acked-by: Matt Ranostay <mranostay@ti.com> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20221031200633.26997-1-j-choudhary@ti.com
2022-11-16arm64: dts: ti: k3-am64-main: Drop RNG clockJayesh Choudhary
The x1-clk used by trng submodule comes directly from the system clock after a fixed divider. It is always running and has a fixed frequency that cannot be changed, making it uncontrollable. Hence this property should be dropped from the rng node. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221107110607.59216-4-j-choudhary@ti.com
2022-11-16arm64: dts: ti: k3-j721e-main: Drop RNG clockJayesh Choudhary
The x1-clk used by trng submodule comes directly from the system clock after a fixed divider. It is always running and has a fixed frequency that cannot be changed, making it uncontrollable. Hence this property should be dropped from the rng node. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221107110607.59216-3-j-choudhary@ti.com
2022-11-16arm64: dts: ti: k3-am65-main: Drop RNG clockJayesh Choudhary
The x1-clk used by trng submodule comes directly from the system clock after a fixed divider. It is always running and has a fixed frequency that cannot be changed, making it uncontrollable. Hence this property should be dropped from the rng node. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221107110607.59216-2-j-choudhary@ti.com
2022-11-16arm64: dts: ti: j721e-common-proc-board: Fix sound node-nameJayesh Choudhary
If root-node has no reg property, the unit-address should not be appended at the end of node-name. 'sound' node has no 'reg' property, so remove the unit-address. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20220928122509.143342-1-j-choudhary@ti.com
2022-11-16arm64: dts: ti: k3-j721s2: Fix the interrupt ranges property for main & wkup ↵Keerthy
gpio intr The parent's input irq number is wrongly subtracted with 32 instead of using the exact numbers in: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721s2/interrupt_cfg.html The GPIO interrupts are not working because of that. The toggling works fine but interrupts are not firing. Fix the parent's input irq that specifies the base for parent irq. Tested for MAIN_GPIO0_6 interrupt on the j721s2 EVM. Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20220922072950.9157-1-j-keerthy@ti.com
2022-11-16ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0Andre Przywara
As many other Allwinner SoCs from the last years, the first USB host controller pair in the Allwinner H3 and H5 chips share a USB PHY with the MUSB OTG controller. This is probably the reason why we didn't have a "phys" property in those host controller nodes. This works fine as long as the MUSB controller driver is loaded, as this takes care of the proper PHY setup, including the muxing between MUSB and the HCI. However this requires the MUSB driver to be enabled and loaded, and also upsets U-Boot, which cannot use a HCI port without a "phys" property. Similar to what we did in commit cc72570747e4 ("arm64: dts: allwinner: A64: properly connect USB PHY to port 0"), add the "phys" property to the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file. This is not only the proper description of the hardware, but also avoids a nasty error message in U-Boot triggered by a recent patch. (The port never worked in host mode, but the error was suppressed due to a bug.) When using the MUSB port in OTG mode, this also fixes host mode switching, so people can use OTG adapters to connect a USB device to port 0. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221110005507.19464-1-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add LRADC nodeAndre Przywara
The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC) compatible to the version in other SoCs. The manual doesn't mention the ratio of the input voltage that is used, but comparing actual measurements with the values in the register suggests that it is 3/4 of Vref. Add the DT node describing the base address and interrupt. As in the older SoCs, there is no explicit reset or clock gate, also there is a dedicated, non-multiplexed pin, so need for more properties. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-8-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add CIR DT nodeAndre Przywara
The CIR (infrared receiver) controller in the Allwinner F1C100s series of SoCs is compatible to the ones used in other Allwinner SoCs. Add the DT node describing the resources of the controller. There are multiple possible pinmuxes, but none as them seem to be an obvious choice, so refrain from adding any pincontroller subnodes for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-7-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16dt-bindings: media: IR: Add F1C100s IR compatible stringAndre Przywara
The CIR controller in the Allwinner F1C100s series of SoCs is compatible to the ones used in other Allwinner SoCs. Add the respective compatible name to the existing IR binding, and pair it with the A31 fallback compatible string. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221107005433.11079-6-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add I2C DT nodesAndre Przywara
The Allwinner F1C100s series of SoCs contain three I2C controllers compatible to the ones used in other Allwinner SoCs. Add the DT nodes describing the resources of the controllers. At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so include those pins already, to simplify referencing them later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add PWM nodeAndre Przywara
The Allwinner F1C100s family of SoCs contain a PWM controller compatible to the one used in the A20 chip. Add the DT node so that any users can simply enable it in their board DT. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-3-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatibleAndre Przywara
The PWM controller in the Allwinner F1C100s series of SoCs is the same as in the A20 SoCs, so allow using that as the fallback name. Join the V3s compatible string in an enum on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20221107005433.11079-2-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-15arm64: dts: broadcom: trim addresses to 8 digitsKrzysztof Kozlowski
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221115105047.95281-1-krzysztof.kozlowski@linaro.org Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-11-15arm64: dts: qcom: sdm845-polaris: Don't duplicate DMA assignmentKonrad Dybcio
The DMA properties in this DT are identical to the ones already defined in sdm845.dtsi. Remove them. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114140011.43442-1-konrad.dybcio@linaro.org
2022-11-15arm64: dts: qcom: sm8350-sagami: Wire up USB regulators and fix USB3Konrad Dybcio
Wire up necessary supplies to USB PHYs to enable USB3 on Sagami and remove all the limit-to-USB2 properties. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114143642.44839-2-konrad.dybcio@linaro.org
2022-11-15arm64: dts: qcom: sm8350-sagami: Add most RPMh regulatorsKonrad Dybcio
Configure most RPMh-controlled regulators on SoMC Sagami. The missing ones (on pm8350b and pm8008[ij]) will be configured when driver support is added. Thankfully, it looks like PDX215 and PDX214 don't have any differences when it comes to PM8350/PM8350C/PMR735a. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114143642.44839-1-konrad.dybcio@linaro.org
2022-11-15arm64: dts: qcom: sc7280: Make herobrine-audio-rt5682 mic dtsi's match moreDouglas Anderson
The 1-mic and 3-mic dtsi still had two minor cosmetic differences after commit '3d11e7e120ee ("arm64: dts: qcom: sc7280: sort out the "Status" to last property with sc7280-herobrine-audio-rt5682.dtsi")'. Let's fix them so the two files diff better. This is expected to have no effect though it will slightly change the generated dtb by removing an unnecessary 'status = "okay"' from the sound node. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114162807.1.I0900b97128f9bb03e5f96fcb3068c227a33f143a@changeid
2022-11-15dt-bindings: arm: add xiaomi,sagit board based on msm8998 chipDzmitry Sankouski
Add xiaomi,sagit board (Xiaomi Mi 6) binding. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221112203300.536010-2-dsankouski@gmail.com
2022-11-15arm64: dts: qcom: trim addresses to 8 digitsKrzysztof Kozlowski
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115105046.95254-1-krzysztof.kozlowski@linaro.org
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