diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2022-11-07 00:54:30 +0000 |
|---|---|---|
| committer | Jernej Skrabec <jernej.skrabec@gmail.com> | 2022-11-16 19:38:28 +0100 |
| commit | dee020350091498fdeb919e35f37bf3f3dca1bdd (patch) | |
| tree | 2ede8add912968953321044299ffdb09f46e5514 | |
| parent | e1d7dc52c3e629540401bf88cbdd8acaa5aea9de (diff) | |
ARM: dts: suniv: f1c100s: add LRADC node
The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
compatible to the version in other SoCs.
The manual doesn't mention the ratio of the input voltage that is used,
but comparing actual measurements with the values in the register
suggests that it is 3/4 of Vref.
Add the DT node describing the base address and interrupt. As in the
older SoCs, there is no explicit reset or clock gate, also there is a
dedicated, non-multiplexed pin, so need for more properties.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-8-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
| -rw-r--r-- | arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 2db99fb352e61..9455d27e516ee 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -254,6 +254,14 @@ status = "disabled"; }; + lradc: lradc@1c23400 { + compatible = "allwinner,suniv-f1c100s-lradc", + "allwinner,sun8i-a83t-r-lradc"; + reg = <0x01c23400 0x400>; + interrupts = <22>; + status = "disabled"; + }; + uart0: serial@1c25000 { compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>; |