diff options
Diffstat (limited to 'drivers/clk/mediatek/clk-mux.h')
| -rw-r--r-- | drivers/clk/mediatek/clk-mux.h | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index 943ad1d7ce4b..151e56dcf884 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -29,10 +29,16 @@ struct mtk_mux { u32 clr_ofs; u32 upd_ofs; + u32 hwv_set_ofs; + u32 hwv_clr_ofs; + u32 hwv_sta_ofs; + u32 fenc_sta_mon_ofs; + u8 mux_shift; u8 mux_width; u8 gate_shift; s8 upd_shift; + u8 fenc_shift; const struct clk_ops *ops; signed char num_parents; @@ -77,6 +83,8 @@ struct mtk_mux { extern const struct clk_ops mtk_mux_clr_set_upd_ops; extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; +extern const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops; +extern const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops; #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ @@ -118,6 +126,85 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; 0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \ mtk_mux_clr_set_upd_ops) +#define MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc, _flags) { \ + .id = _id, \ + .name = _name, \ + .mux_ofs = _mux_ofs, \ + .set_ofs = _mux_set_ofs, \ + .clr_ofs = _mux_clr_ofs, \ + .hwv_sta_ofs = _hwv_sta_ofs, \ + .hwv_set_ofs = _hwv_set_ofs, \ + .hwv_clr_ofs = _hwv_clr_ofs, \ + .upd_ofs = _upd_ofs, \ + .fenc_sta_mon_ofs = _fenc_sta_mon_ofs, \ + .mux_shift = _shift, \ + .mux_width = _width, \ + .gate_shift = _gate, \ + .upd_shift = _upd, \ + .fenc_shift = _fenc, \ + .parent_names = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = _flags, \ + .ops = &mtk_mux_gate_hwv_fenc_clr_set_upd_ops, \ + } + +#define MUX_GATE_HWV_FENC_CLR_SET_UPD(_id, _name, _parents, \ + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc) \ + MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc, 0) + +#define MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ + _num_parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc, _flags) { \ + .id = _id, \ + .name = _name, \ + .mux_ofs = _mux_ofs, \ + .set_ofs = _mux_set_ofs, \ + .clr_ofs = _mux_clr_ofs, \ + .upd_ofs = _upd_ofs, \ + .fenc_sta_mon_ofs = _fenc_sta_mon_ofs, \ + .mux_shift = _shift, \ + .mux_width = _width, \ + .gate_shift = _gate, \ + .upd_shift = _upd, \ + .fenc_shift = _fenc, \ + .parent_names = _parents, \ + .parent_index = _paridx, \ + .num_parents = _num_parents, \ + .flags = _flags, \ + .ops = &mtk_mux_gate_fenc_clr_set_upd_ops, \ + } + +#define MUX_GATE_FENC_CLR_SET_UPD(_id, _name, _parents, \ + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc) \ + MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ + NULL, ARRAY_SIZE(_parents), _mux_ofs, \ + _mux_set_ofs, _mux_clr_ofs, _shift, \ + _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc, 0) + +#define MUX_GATE_FENC_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \ + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc) \ + MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ + ARRAY_SIZE(_paridx), _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc, 0) + int mtk_clk_register_muxes(struct device *dev, const struct mtk_mux *muxes, int num, struct device_node *node, |