diff options
Diffstat (limited to 'Documentation/devicetree/bindings/crypto')
25 files changed, 644 insertions, 473 deletions
diff --git a/Documentation/devicetree/bindings/crypto/amd,ccp-seattle-v1a.yaml b/Documentation/devicetree/bindings/crypto/amd,ccp-seattle-v1a.yaml new file mode 100644 index 0000000000000..32bf3a1c3b420 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/amd,ccp-seattle-v1a.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/amd,ccp-seattle-v1a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Cryptographic Coprocessor (ccp) + +maintainers: + - Tom Lendacky <thomas.lendacky@amd.com> + +properties: + compatible: + const: amd,ccp-seattle-v1a + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + crypto@e0100000 { + compatible = "amd,ccp-seattle-v1a"; + reg = <0xe0100000 0x10000>; + interrupts = <0 3 4>; + dma-coherent; + }; diff --git a/Documentation/devicetree/bindings/crypto/amd-ccp.txt b/Documentation/devicetree/bindings/crypto/amd-ccp.txt deleted file mode 100644 index d87579d63da64..0000000000000 --- a/Documentation/devicetree/bindings/crypto/amd-ccp.txt +++ /dev/null @@ -1,17 +0,0 @@ -* AMD Cryptographic Coprocessor driver (ccp) - -Required properties: -- compatible: Should be "amd,ccp-seattle-v1a" -- reg: Address and length of the register set for the device -- interrupts: Should contain the CCP interrupt - -Optional properties: -- dma-coherent: Present if dma operations are coherent - -Example: - ccp@e0100000 { - compatible = "amd,ccp-seattle-v1a"; - reg = <0 0xe0100000 0 0x10000>; - interrupt-parent = <&gic>; - interrupts = <0 3 4>; - }; diff --git a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt deleted file mode 100644 index d9cca4875bd64..0000000000000 --- a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt +++ /dev/null @@ -1,16 +0,0 @@ -Axis crypto engine with PDMA interface. - -Required properties: -- compatible : Should be one of the following strings: - "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC - "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC. -- reg: Base address and size for the PDMA register area. -- interrupts: Interrupt handle for the PDMA interrupt line. - -Example: - -crypto@f4264000 { - compatible = "axis,artpec6-crypto"; - reg = <0xf4264000 0x1000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml index 7dc0748444fde..19010f90198a1 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml @@ -15,7 +15,9 @@ properties: oneOf: - const: atmel,at91sam9g46-aes - items: - - const: microchip,sam9x7-aes + - enum: + - microchip,sam9x7-aes + - microchip,sama7d65-aes - const: atmel,at91sam9g46-aes reg: diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml index d378c53314dd0..39e076b275b39 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml @@ -15,7 +15,9 @@ properties: oneOf: - const: atmel,at91sam9g46-sha - items: - - const: microchip,sam9x7-sha + - enum: + - microchip,sam9x7-sha + - microchip,sama7d65-sha - const: atmel,at91sam9g46-sha reg: diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml index 6a441f79efea5..6f16008c4251c 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml @@ -15,7 +15,9 @@ properties: oneOf: - const: atmel,at91sam9g46-tdes - items: - - const: microchip,sam9x7-tdes + - enum: + - microchip,sam9x7-tdes + - microchip,sama7d65-tdes - const: atmel,at91sam9g46-tdes reg: diff --git a/Documentation/devicetree/bindings/crypto/axis,artpec6-crypto.yaml b/Documentation/devicetree/bindings/crypto/axis,artpec6-crypto.yaml new file mode 100644 index 0000000000000..c91f81e3c39e6 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/axis,artpec6-crypto.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/axis,artpec6-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC6 crypto engine with PDMA interface + +maintainers: + - Lars Persson <lars.persson@axis.com> + +properties: + compatible: + enum: + - axis,artpec6-crypto + - axis,artpec7-crypto + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + crypto@f4264000 { + compatible = "axis,artpec6-crypto"; + reg = <0xf4264000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt b/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt deleted file mode 100644 index 29b6007568eb3..0000000000000 --- a/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt +++ /dev/null @@ -1,22 +0,0 @@ -The Broadcom Secure Processing Unit (SPU) hardware supports symmetric -cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware -blocks. - -Required properties: -- compatible: Should be one of the following: - brcm,spum-crypto - for devices with SPU-M hardware - brcm,spu2-crypto - for devices with SPU2 hardware - brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3 - and Rabin Fingerprint support - brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware - -- reg: Should contain SPU registers location and length. -- mboxes: The mailbox channel to be used to communicate with the SPU. - Mailbox channels correspond to DMA rings on the device. - -Example: - crypto@612d0000 { - compatible = "brcm,spum-crypto"; - reg = <0 0x612d0000 0 0x900>; - mboxes = <&pdc0 0>; - }; diff --git a/Documentation/devicetree/bindings/crypto/brcm,spum-crypto.yaml b/Documentation/devicetree/bindings/crypto/brcm,spum-crypto.yaml new file mode 100644 index 0000000000000..9a5fb61727fa5 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/brcm,spum-crypto.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/brcm,spum-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom SPU Crypto Offload + +maintainers: + - Rob Rice <rob.rice@broadcom.com> + +description: + The Broadcom Secure Processing Unit (SPU) hardware supports symmetric + cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware + blocks. + +properties: + compatible: + enum: + - brcm,spum-crypto + - brcm,spu2-crypto + - brcm,spu2-v2-crypto # enhanced SPU2 hardware features like SHA3 and Rabin Fingerprint support + - brcm,spum-nsp-crypto # Northstar Plus variant of the SPU-M hardware + + reg: + maxItems: 1 + + mboxes: + maxItems: 1 + +required: + - compatible + - reg + - mboxes + +additionalProperties: false + +examples: + - | + crypto@612d0000 { + compatible = "brcm,spum-crypto"; + reg = <0x612d0000 0x900>; + mboxes = <&pdc0 0>; + }; diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml index e879bc0be8e22..9f8e6689cd947 100644 --- a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml @@ -83,6 +83,8 @@ properties: by SNVS ONOFF, the driver can report the status of POWER key and wakeup system if pressed after system suspend. + $ref: /schemas/input/input.yaml + properties: compatible: const: fsl,sec-v4.0-pwrkey @@ -111,6 +113,9 @@ properties: maxItems: 1 default: 116 + power-off-time-sec: + enum: [0, 5, 10, 15] + required: - compatible - interrupts diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml index f0c4a7c83568a..dcc755d2709a7 100644 --- a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml @@ -38,12 +38,16 @@ properties: compatible: oneOf: - items: - - const: fsl,sec-v5.4 + - enum: + - fsl,sec-v5.4 + - fsl,sec-v6.0 - const: fsl,sec-v5.0 - const: fsl,sec-v4.0 - items: - enum: - fsl,imx6ul-caam + - fsl,imx8qm-caam + - fsl,imx8qxp-caam - fsl,sec-v5.0 - const: fsl,sec-v4.0 - const: fsl,sec-v4.0 @@ -75,6 +79,9 @@ properties: interrupts: maxItems: 1 + power-domains: + maxItems: 1 + fsl,sec-era: description: Defines the 'ERA' of the SEC device. $ref: /schemas/types.yaml#/definitions/uint32 @@ -94,12 +101,21 @@ patternProperties: compatible: oneOf: - items: - - const: fsl,sec-v5.4-job-ring + - const: fsl,sec-v6.0-job-ring + - const: fsl,sec-v5.2-job-ring - const: fsl,sec-v5.0-job-ring + - const: fsl,sec-v4.4-job-ring - const: fsl,sec-v4.0-job-ring - items: + - const: fsl,sec-v5.4-job-ring - const: fsl,sec-v5.0-job-ring - const: fsl,sec-v4.0-job-ring + - items: + - enum: + - fsl,imx8qm-job-ring + - fsl,imx8qxp-job-ring + - fsl,sec-v5.0-job-ring + - const: fsl,sec-v4.0-job-ring - const: fsl,sec-v4.0-job-ring reg: @@ -108,6 +124,9 @@ patternProperties: interrupts: maxItems: 1 + power-domains: + maxItems: 1 + fsl,liodn: description: Specifies the LIODN to be used in conjunction with the ppid-to-liodn @@ -117,6 +136,20 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32-array items: - maximum: 0xfff + allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-job-ring + - fsl,imx8qxp-job-ring + then: + required: + - power-domains + else: + properties: + power-domains: false '^rtic@[0-9a-f]+$': type: object @@ -204,6 +237,20 @@ required: - reg - ranges +if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-caam + - fsl,imx8qxp-caam +then: + required: + - power-domains +else: + properties: + power-domains: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt deleted file mode 100644 index 73b0eb950bb39..0000000000000 --- a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt +++ /dev/null @@ -1,157 +0,0 @@ -SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM). -Currently Freescale powerpc chip C29X is embedded with SEC 6. -SEC 6 device tree binding include: - -SEC 6 Node - -Job Ring Node - -Full Example - -===================================================================== -SEC 6 Node - -Description - - Node defines the base address of the SEC 6 block. - This block specifies the address range of all global - configuration registers for the SEC 6 block. - For example, In C293, we could see three SEC 6 node. - -PROPERTIES - - - compatible - Usage: required - Value type: <string> - Definition: Must include "fsl,sec-v6.0". - - - fsl,sec-era - Usage: optional - Value type: <u32> - Definition: A standard property. Define the 'ERA' of the SEC - device. - - - #address-cells - Usage: required - Value type: <u32> - Definition: A standard property. Defines the number of cells - for representing physical addresses in child nodes. - - - #size-cells - Usage: required - Value type: <u32> - Definition: A standard property. Defines the number of cells - for representing the size of physical addresses in - child nodes. - - - reg - Usage: required - Value type: <prop-encoded-array> - Definition: A standard property. Specifies the physical - address and length of the SEC 6 configuration registers. - - - ranges - Usage: required - Value type: <prop-encoded-array> - Definition: A standard property. Specifies the physical address - range of the SEC 6.0 register space (-SNVS not included). A - triplet that includes the child address, parent address, & - length. - - Note: All other standard properties (see the Devicetree Specification) - are allowed but are optional. - -EXAMPLE - crypto@a0000 { - compatible = "fsl,sec-v6.0"; - fsl,sec-era = <6>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xa0000 0x20000>; - ranges = <0 0xa0000 0x20000>; - }; - -===================================================================== -Job Ring (JR) Node - - Child of the crypto node defines data processing interface to SEC 6 - across the peripheral bus for purposes of processing - cryptographic descriptors. The specified address - range can be made visible to one (or more) cores. - The interrupt defined for this node is controlled within - the address range of this node. - - - compatible - Usage: required - Value type: <string> - Definition: Must include "fsl,sec-v6.0-job-ring". - - - reg - Usage: required - Value type: <prop-encoded-array> - Definition: Specifies a two JR parameters: an offset from - the parent physical address and the length the JR registers. - - - interrupts - Usage: required - Value type: <prop_encoded-array> - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - -EXAMPLE - jr@1000 { - compatible = "fsl,sec-v6.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = <49 2 0 0>; - }; - -=================================================================== -Full Example - -Since some chips may contain more than one SEC, the dtsi contains -only the node contents, not the node itself. A chip using the SEC -should include the dtsi inside each SEC node. Example: - -In qoriq-sec6.0.dtsi: - - compatible = "fsl,sec-v6.0"; - fsl,sec-era = <6>; - #address-cells = <1>; - #size-cells = <1>; - - jr@1000 { - compatible = "fsl,sec-v6.0-job-ring", - "fsl,sec-v5.2-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.4-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - }; - - jr@2000 { - compatible = "fsl,sec-v6.0-job-ring", - "fsl,sec-v5.2-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.4-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - }; - -In the C293 device tree, we add the include of public property: - - crypto@a0000 { - /include/ "qoriq-sec6.0.dtsi" - } - - crypto@a0000 { - reg = <0xa0000 0x20000>; - ranges = <0 0xa0000 0x20000>; - - jr@1000 { - interrupts = <49 2 0 0>; - }; - - jr@2000 { - interrupts = <50 2 0 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml b/Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml new file mode 100644 index 0000000000000..2bfac9d1c020a --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/hisilicon,hip06-sec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon hip06/hip07 Security Accelerator + +maintainers: + - Jonathan Cameron <Jonathan.Cameron@huawei.com> + +properties: + compatible: + enum: + - hisilicon,hip06-sec + - hisilicon,hip07-sec + + reg: + items: + - description: Registers for backend processing engines + - description: Registers for common functionality + - description: Registers for queue 0 + - description: Registers for queue 1 + - description: Registers for queue 2 + - description: Registers for queue 3 + - description: Registers for queue 4 + - description: Registers for queue 5 + - description: Registers for queue 6 + - description: Registers for queue 7 + - description: Registers for queue 8 + - description: Registers for queue 9 + - description: Registers for queue 10 + - description: Registers for queue 11 + - description: Registers for queue 12 + - description: Registers for queue 13 + - description: Registers for queue 14 + - description: Registers for queue 15 + + interrupts: + items: + - description: SEC unit error queue interrupt + - description: Completion interrupt for queue 0 + - description: Error interrupt for queue 0 + - description: Completion interrupt for queue 1 + - description: Error interrupt for queue 1 + - description: Completion interrupt for queue 2 + - description: Error interrupt for queue 2 + - description: Completion interrupt for queue 3 + - description: Error interrupt for queue 3 + - description: Completion interrupt for queue 4 + - description: Error interrupt for queue 4 + - description: Completion interrupt for queue 5 + - description: Error interrupt for queue 5 + - description: Completion interrupt for queue 6 + - description: Error interrupt for queue 6 + - description: Completion interrupt for queue 7 + - description: Error interrupt for queue 7 + - description: Completion interrupt for queue 8 + - description: Error interrupt for queue 8 + - description: Completion interrupt for queue 9 + - description: Error interrupt for queue 9 + - description: Completion interrupt for queue 10 + - description: Error interrupt for queue 10 + - description: Completion interrupt for queue 11 + - description: Error interrupt for queue 11 + - description: Completion interrupt for queue 12 + - description: Error interrupt for queue 12 + - description: Completion interrupt for queue 13 + - description: Error interrupt for queue 13 + - description: Completion interrupt for queue 14 + - description: Error interrupt for queue 14 + - description: Completion interrupt for queue 15 + - description: Error interrupt for queue 15 + + dma-coherent: true + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - dma-coherent + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + crypto@400d2000000 { + compatible = "hisilicon,hip07-sec"; + reg = <0x400 0xd0000000 0x0 0x10000 + 0x400 0xd2000000 0x0 0x10000 + 0x400 0xd2010000 0x0 0x10000 + 0x400 0xd2020000 0x0 0x10000 + 0x400 0xd2030000 0x0 0x10000 + 0x400 0xd2040000 0x0 0x10000 + 0x400 0xd2050000 0x0 0x10000 + 0x400 0xd2060000 0x0 0x10000 + 0x400 0xd2070000 0x0 0x10000 + 0x400 0xd2080000 0x0 0x10000 + 0x400 0xd2090000 0x0 0x10000 + 0x400 0xd20a0000 0x0 0x10000 + 0x400 0xd20b0000 0x0 0x10000 + 0x400 0xd20c0000 0x0 0x10000 + 0x400 0xd20d0000 0x0 0x10000 + 0x400 0xd20e0000 0x0 0x10000 + 0x400 0xd20f0000 0x0 0x10000 + 0x400 0xd2100000 0x0 0x10000>; + interrupts = <576 4>, + <577 1>, <578 4>, + <579 1>, <580 4>, + <581 1>, <582 4>, + <583 1>, <584 4>, + <585 1>, <586 4>, + <587 1>, <588 4>, + <589 1>, <590 4>, + <591 1>, <592 4>, + <593 1>, <594 4>, + <595 1>, <596 4>, + <597 1>, <598 4>, + <599 1>, <600 4>, + <601 1>, <602 4>, + <603 1>, <604 4>, + <605 1>, <606 4>, + <607 1>, <608 4>; + dma-coherent; + iommus = <&p1_smmu_alg_a 0x600>; + }; + }; diff --git a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt deleted file mode 100644 index d28fd1af01b40..0000000000000 --- a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Hisilicon hip07 Security Accelerator (SEC) - -Required properties: -- compatible: Must contain one of - - "hisilicon,hip06-sec" - - "hisilicon,hip07-sec" -- reg: Memory addresses and lengths of the memory regions through which - this device is controlled. - Region 0 has registers to control the backend processing engines. - Region 1 has registers for functionality common to all queues. - Regions 2-18 have registers for the 16 individual queues which are isolated - both in hardware and within the driver. -- interrupts: Interrupt specifiers. - Refer to interrupt-controller/interrupts.txt for generic interrupt client node - bindings. - Interrupt 0 is for the SEC unit error queue. - Interrupt 2N + 1 is the completion interrupt for queue N. - Interrupt 2N + 2 is the error interrupt for queue N. -- dma-coherent: The driver assumes coherent dma is possible. - -Optional properties: -- iommus: The SEC units are behind smmu-v3 iommus. - Refer to iommu/arm,smmu-v3.txt for more information. - -Example: - -p1_sec_a: crypto@400d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x400 0xd0000000 0x0 0x10000 - 0x400 0xd2000000 0x0 0x10000 - 0x400 0xd2010000 0x0 0x10000 - 0x400 0xd2020000 0x0 0x10000 - 0x400 0xd2030000 0x0 0x10000 - 0x400 0xd2040000 0x0 0x10000 - 0x400 0xd2050000 0x0 0x10000 - 0x400 0xd2060000 0x0 0x10000 - 0x400 0xd2070000 0x0 0x10000 - 0x400 0xd2080000 0x0 0x10000 - 0x400 0xd2090000 0x0 0x10000 - 0x400 0xd20a0000 0x0 0x10000 - 0x400 0xd20b0000 0x0 0x10000 - 0x400 0xd20c0000 0x0 0x10000 - 0x400 0xd20d0000 0x0 0x10000 - 0x400 0xd20e0000 0x0 0x10000 - 0x400 0xd20f0000 0x0 0x10000 - 0x400 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p1_mbigen_sec_a>; - iommus = <&p1_smmu_alg_a 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; -}; diff --git a/Documentation/devicetree/bindings/crypto/img,hash-accelerator.yaml b/Documentation/devicetree/bindings/crypto/img,hash-accelerator.yaml new file mode 100644 index 0000000000000..46617561ef947 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/img,hash-accelerator.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/img,hash-accelerator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination Technologies hardware hash accelerator + +maintainers: + - James Hartley <james.hartley@imgtec.com> + +description: + The hash accelerator provides hardware hashing acceleration for + SHA1, SHA224, SHA256 and MD5 hashes. + +properties: + compatible: + const: img,hash-accelerator + + reg: + items: + - description: Register base address and size + - description: DMA port specifier + + interrupts: + maxItems: 1 + + dmas: + maxItems: 1 + + dma-names: + items: + - const: tx + + clocks: + items: + - description: System clock for hash block registers + - description: Hash clock for data path + + clock-names: + items: + - const: sys + - const: hash + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - dmas + - dma-names + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/clock/pistachio-clk.h> + + hash@18149600 { + compatible = "img,hash-accelerator"; + reg = <0x18149600 0x100>, <0x18101100 0x4>; + interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma 8 0xffffffff 0>; + dma-names = "tx"; + clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>; + clock-names = "sys", "hash"; + }; diff --git a/Documentation/devicetree/bindings/crypto/img-hash.txt b/Documentation/devicetree/bindings/crypto/img-hash.txt deleted file mode 100644 index 91a3d757d641b..0000000000000 --- a/Documentation/devicetree/bindings/crypto/img-hash.txt +++ /dev/null @@ -1,27 +0,0 @@ -Imagination Technologies hardware hash accelerator - -The hash accelerator provides hardware hashing acceleration for -SHA1, SHA224, SHA256 and MD5 hashes - -Required properties: - -- compatible : "img,hash-accelerator" -- reg : Offset and length of the register set for the module, and the DMA port -- interrupts : The designated IRQ line for the hashing module. -- dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt -- dma-names : Should be "tx" -- clocks : Clock specifiers -- clock-names : "sys" Used to clock the hash block registers - "hash" Used to clock data through the accelerator - -Example: - - hash: hash@18149600 { - compatible = "img,hash-accelerator"; - reg = <0x18149600 0x100>, <0x18101100 0x4>; - interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dma 8 0xffffffff 0>; - dma-names = "tx"; - clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>; - clock-names = "sys", "hash"; - }; diff --git a/Documentation/devicetree/bindings/crypto/marvell,orion-crypto.yaml b/Documentation/devicetree/bindings/crypto/marvell,orion-crypto.yaml new file mode 100644 index 0000000000000..b44d36c50ec46 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/marvell,orion-crypto.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/marvell,orion-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Cryptographic Engines And Security Accelerator + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Boris Brezillon <bbrezillon@kernel.org> + +description: | + Marvell Cryptographic Engines And Security Accelerator + +properties: + compatible: + enum: + - marvell,armada-370-crypto + - marvell,armada-xp-crypto + - marvell,armada-375-crypto + - marvell,armada-38x-crypto + - marvell,dove-crypto + - marvell,kirkwood-crypto + - marvell,orion-crypto + + reg: + minItems: 1 + items: + - description: Registers region + - description: SRAM region + deprecated: true + + reg-names: + minItems: 1 + items: + - const: regs + - const: sram + deprecated: true + + interrupts: + description: One interrupt for each CESA engine + minItems: 1 + maxItems: 2 + + clocks: + description: One or two clocks for each CESA engine + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + items: + - const: cesa0 + - const: cesa1 + - const: cesaz0 + - const: cesaz1 + + marvell,crypto-srams: + description: Phandle(s) to crypto SRAM. + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 2 + items: + maxItems: 1 + + marvell,crypto-sram-size: + description: SRAM size reserved for crypto operations. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x800 + +required: + - compatible + - reg + - reg-names + - interrupts + - marvell,crypto-srams + +allOf: + - if: + not: + properties: + compatible: + enum: + - marvell,kirkwood-crypto + - marvell,orion-crypto + then: + required: + - clocks + - if: + properties: + compatible: + contains: + enum: + - marvell,armada-370-crypto + - marvell,armada-375-crypto + - marvell,armada-38x-crypto + - marvell,armada-xp-crypto + then: + required: + - clock-names + - if: + properties: + compatible: + contains: + enum: + - marvell,armada-375-crypto + - marvell,armada-38x-crypto + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + else: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + +additionalProperties: false + +examples: + - | + crypto@30000 { + compatible = "marvell,orion-crypto"; + reg = <0x30000 0x10000>; + reg-names = "regs"; + interrupts = <22>; + marvell,crypto-srams = <&crypto_sram>; + marvell,crypto-sram-size = <0x600>; + }; diff --git a/Documentation/devicetree/bindings/crypto/marvell-cesa.txt b/Documentation/devicetree/bindings/crypto/marvell-cesa.txt deleted file mode 100644 index 28d3f2496b892..0000000000000 --- a/Documentation/devicetree/bindings/crypto/marvell-cesa.txt +++ /dev/null @@ -1,44 +0,0 @@ -Marvell Cryptographic Engines And Security Accelerator - -Required properties: -- compatible: should be one of the following string - "marvell,orion-crypto" - "marvell,kirkwood-crypto" - "marvell,dove-crypto" - "marvell,armada-370-crypto" - "marvell,armada-xp-crypto" - "marvell,armada-375-crypto" - "marvell,armada-38x-crypto" -- reg: base physical address of the engine and length of memory mapped - region. Can also contain an entry for the SRAM attached to the CESA, - but this representation is deprecated and marvell,crypto-srams should - be used instead -- reg-names: "regs". Can contain an "sram" entry, but this representation - is deprecated and marvell,crypto-srams should be used instead -- interrupts: interrupt number -- clocks: reference to the crypto engines clocks. This property is not - required for orion and kirkwood platforms -- clock-names: "cesaX" and "cesazX", X should be replaced by the crypto engine - id. - This property is not required for the orion and kirkwoord - platforms. - "cesazX" clocks are not required on armada-370 platforms -- marvell,crypto-srams: phandle to crypto SRAM definitions - -Optional properties: -- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not - specified the whole SRAM is used (2KB) - - -Examples: - - crypto@90000 { - compatible = "marvell,armada-xp-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <48>, <49>; - clocks = <&gateclk 23>, <&gateclk 23>; - clock-names = "cesa0", "cesa1"; - marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>; - marvell,crypto-sram-size = <0x600>; - }; diff --git a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt deleted file mode 100644 index 450da3661cad9..0000000000000 --- a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek cryptographic accelerators - -Required properties: -- compatible: Should be "mediatek,eip97-crypto" -- reg: Address and length of the register set for the device -- interrupts: Should contain the five crypto engines interrupts in numeric - order. These are global system and four descriptor rings. -- clocks: the clock used by the core -- clock-names: Must contain "cryp". -- power-domains: Must contain a reference to the PM domain. - - -Example: - crypto: crypto@1b240000 { - compatible = "mediatek,eip97-crypto"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "cryp"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - }; diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt deleted file mode 100644 index d9b92e2f31381..0000000000000 --- a/Documentation/devicetree/bindings/crypto/mv_cesa.txt +++ /dev/null @@ -1,32 +0,0 @@ -Marvell Cryptographic Engines And Security Accelerator - -Required properties: -- compatible: should be one of the following string - "marvell,orion-crypto" - "marvell,kirkwood-crypto" - "marvell,dove-crypto" -- reg: base physical address of the engine and length of memory mapped - region. Can also contain an entry for the SRAM attached to the CESA, - but this representation is deprecated and marvell,crypto-srams should - be used instead -- reg-names: "regs". Can contain an "sram" entry, but this representation - is deprecated and marvell,crypto-srams should be used instead -- interrupts: interrupt number -- clocks: reference to the crypto engines clocks. This property is only - required for Dove platforms -- marvell,crypto-srams: phandle to crypto SRAM definitions - -Optional properties: -- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not - specified the whole SRAM is used (2KB) - -Examples: - - crypto@30000 { - compatible = "marvell,orion-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <22>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x600>; - }; diff --git a/Documentation/devicetree/bindings/crypto/omap-aes.txt b/Documentation/devicetree/bindings/crypto/omap-aes.txt deleted file mode 100644 index fd9717653cbb9..0000000000000 --- a/Documentation/devicetree/bindings/crypto/omap-aes.txt +++ /dev/null @@ -1,31 +0,0 @@ -OMAP SoC AES crypto Module - -Required properties: - -- compatible : Should contain entries for this and backward compatible - AES versions: - - "ti,omap2-aes" for OMAP2. - - "ti,omap3-aes" for OMAP3. - - "ti,omap4-aes" for OMAP4 and AM33XX. - Note that the OMAP2 and 3 versions are compatible (OMAP3 supports - more algorithms) but they are incompatible with OMAP4. -- ti,hwmods: Name of the hwmod associated with the AES module -- reg : Offset and length of the register set for the module -- interrupts : the interrupt-specifier for the AES module. - -Optional properties: -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: DMA request names should include "tx" and "rx" if present. - -Example: - /* AM335x */ - aes: aes@53500000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; - reg = <0x53500000 0xa0>; - interrupts = <102>; - dmas = <&edma 6>, - <&edma 5>; - dma-names = "tx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/crypto/omap-des.txt b/Documentation/devicetree/bindings/crypto/omap-des.txt deleted file mode 100644 index e8c63bf2e16db..0000000000000 --- a/Documentation/devicetree/bindings/crypto/omap-des.txt +++ /dev/null @@ -1,30 +0,0 @@ -OMAP SoC DES crypto Module - -Required properties: - -- compatible : Should contain "ti,omap4-des" -- ti,hwmods: Name of the hwmod associated with the DES module -- reg : Offset and length of the register set for the module -- interrupts : the interrupt-specifier for the DES module -- clocks : A phandle to the functional clock node of the DES module - corresponding to each entry in clock-names -- clock-names : Name of the functional clock, should be "fck" - -Optional properties: -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt - Each entry corresponds to an entry in dma-names -- dma-names: DMA request names should include "tx" and "rx" if present - -Example: - /* DRA7xx SoC */ - des: des@480a5000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x480a5000 0xa0>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 117>, <&sdma 116>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml index 3f35122f7873c..e009cb712fb8a 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -45,6 +45,7 @@ properties: - items: - enum: + - qcom,qcs615-qce - qcom,qcs8300-qce - qcom,sa8775p-qce - qcom,sc7280-qce diff --git a/Documentation/devicetree/bindings/crypto/ti,omap2-aes.yaml b/Documentation/devicetree/bindings/crypto/ti,omap2-aes.yaml new file mode 100644 index 0000000000000..90e92050ad2eb --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/ti,omap2-aes.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ti,omap2-aes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP SoC AES crypto Module + +maintainers: + - Aaro Koskinen <aaro.koskinen@iki.fi> + - Andreas Kemnade <andreas@kemnade.info> + - Kevin Hilman <khilman@baylibre.com> + - Roger Quadros <rogerq@kernel.org> + - Tony Lindgren <tony@atomide.com> + +properties: + compatible: + enum: + - ti,omap2-aes + - ti,omap3-aes + - ti,omap4-aes + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + ti,hwmods: + description: Name of the hwmod associated with the AES module + const: aes + deprecated: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + aes@53500000 { + compatible = "ti,omap4-aes"; + reg = <0x53500000 0xa0>; + interrupts = <102>; + dmas = <&edma 6>, + <&edma 5>; + dma-names = "tx", "rx"; + }; diff --git a/Documentation/devicetree/bindings/crypto/ti,omap4-des.yaml b/Documentation/devicetree/bindings/crypto/ti,omap4-des.yaml new file mode 100644 index 0000000000000..f02f1e141218d --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/ti,omap4-des.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ti,omap4-des.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP4 DES crypto Module + +maintainers: + - Aaro Koskinen <aaro.koskinen@iki.fi> + - Andreas Kemnade <andreas@kemnade.info> + - Kevin Hilman <khilman@baylibre.com> + - Roger Quadros <rogerq@kernel.org> + - Tony Lindgren <tony@atomide.com> + +properties: + compatible: + const: ti,omap4-des + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + clocks: + maxItems: 1 + + clock-names: + items: + - const: fck + +dependencies: + dmas: [ dma-names ] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + des@480a5000 { + compatible = "ti,omap4-des"; + reg = <0x480a5000 0xa0>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + dmas = <&sdma 117>, <&sdma 116>; + dma-names = "tx", "rx"; + }; |