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authorSakari Ailus <sakari.ailus@linux.intel.com>2020-07-07 10:08:01 +0200
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>2020-12-07 15:49:01 +0100
commitfe52ece8d2e26bd4d38e2c99a7cd13d944c1ee98 (patch)
tree2e53bbb49e28841693b20defa2bd79dc06cefed7 /tools/perf/scripts/python
parentcab27256e8b3a6529faab9fc00e40fcf60b16590 (diff)
media: ccs-pll: Fix condition for pre-PLL divider lower bound
The lower bound of the pre-PLL divider was calculated based on OP SYS clock frequency which is also affected by the OP SYS clock divider. This is wrong. The right clock frequency is that of the PLL output clock. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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