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authorClément Léger <clement.leger@bootlin.com>2022-06-24 16:39:58 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2022-06-29 15:28:39 +0200
commitc6f600923600e7af24efab1697a859d1d2389c66 (patch)
tree04073320a09fc3447031d2f41934a48390e8a2cd /tools/perf/scripts/python
parentdc0f67311416c86ed3c6f14a365c8e833ed4b8dd (diff)
ARM: dts: r9a06g032: Describe GMAC2
The RZ/N1 SoC includes two MACs named GMACx that are compatible with the "snps,dwmac" driver. GMAC1 is connected directly to the MII converter port 1. GMAC2 however can be used as the MAC for the switch CPU management port or can be muxed to be connected directly to the MII converter port 2. This commit adds the description for the GMAC2 which will be used by the switch description. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20220624144001.95518-14-clement.leger@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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