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author | Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2024-11-21 14:41:05 +0100 |
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committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2024-12-19 12:50:14 +0100 |
commit | 91a7088096a49eb413ca11a9d80bc8ba60695c18 (patch) | |
tree | 93ea7a832fea8de4f41468894f96ac05fb6d8bcb /tools/perf/scripts/python | |
parent | 57d10bcac67707caaa542e09dee86e13ea85defc (diff) |
media: dt-bindings: Add property to describe CSI-2 C-PHY line orders
Each data lane on a CSI-2 C-PHY bus uses three phase encoding and is
constructed from three physical wires. The wires are referred to as A, B
and C and their default order is ABC. However to ease hardware design
the specification allows for the wires to be switched in any order.
Add a vendor neutral property to describe the line order used. The
property name 'line-orders', the possible values it can be assigned and
there names are taken from the MIPI Discovery and Configuration (DisCo)
Specification for Imaging.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions