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authorTaniya Das <quic_tdas@quicinc.com>2025-07-02 14:34:21 +0530
committerBjorn Andersson <andersson@kernel.org>2025-07-16 23:12:05 -0500
commit48d2c6dec1c46460ee7028915595d49a644e8a77 (patch)
tree84b44a17db4e5951e2fe08ba35fedc4533fca3ab /tools/perf/scripts/python
parentf6a4a55ae5d99f865e106916a9295548e381de47 (diff)
clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs
The alpha PLLs which slew to a new frequency at runtime would require the PLL to calibrate at the mid point of the VCO. Add the new PLL ops which can support the slewing of the PLL to a new frequency. Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-1-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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