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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-06-27 16:51:14 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-08-09 09:53:47 +0200 |
| commit | b51d5275016c6edbf4656eaee30d836fef127016 (patch) | |
| tree | cf8c1fb3ef2b4ad4e8e944b5b582b1c31cb135f7 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 2570d4005d475818711c96e83fb84d5048ab8e1b (diff) | |
clk: renesas: r8a7796: Add watchdog module clock
Add the module clock for the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions