diff options
| author | George Moussalem <george.moussalem@outlook.com> | 2025-05-16 16:36:09 +0400 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-07-16 23:03:27 -0500 |
| commit | 314b903c30040632db7edd187cd33003b2aee512 (patch) | |
| tree | 806ef7e2dc069fd6167331c9e8de617f1238307b /tools/perf/scripts/python/stackcollapse.py | |
| parent | 19272b37aa4f83ca52bdf9c16d5d81bdd1354494 (diff) | |
dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
ethernet (50Mhz) clocks.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions