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authorCristian Ciocaltea <cristian.ciocaltea@collabora.com>2025-06-12 00:47:47 +0300
committerHeiko Stuebner <heiko@sntech.de>2025-06-30 11:12:44 +0200
commit3832dc42aed9b047ccecebf5917d008bd2dac940 (patch)
treee7fd61d283f229e65225f77f978b7d5aa6783637 /tools/perf/scripts/python/sched-migration.py
parent8733bf4c46f2546bc9225951ae2fee306bbb8e25 (diff)
dt-bindings: display: vop2: Add optional PLL clock property for rk3576
As with the RK3588 SoC, RK3576 also allows the use of HDMI PHY PLL as an alternative and more accurate pixel clock source for VOP2. Document the optional PLL clock property. Moreover, given that this is part of a series intended to address some recent display problems, provide the appropriate tags to facilitate backporting. Fixes: c3b7c5a4d7c1 ("dt-bindings: display: vop2: Add rk3576 support") Cc: stable@vger.kernel.org Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-1-4b11007d8675@collabora.com
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