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| author | Matt Roper <matthew.d.roper@intel.com> | 2021-07-21 15:30:37 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-22 09:29:20 -0700 |
| commit | 87fc875a2b85043f9cc34f84e1beb2ec51a9e5d3 (patch) | |
| tree | 0b23f9cc9d898bb0dfcb822182494a459f5cf643 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 1f3e84c4edcd357eeb608d709c9c2dcb3193c841 (diff) | |
drm/i915/dg2: Skip shared DPLL handling
DG2 has no shared DPLL's or DDI clock muxing. The Port PLL is embedded
within the PHY.
Bspec: 54032
Bspec: 54034
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-13-matthew.d.roper@intel.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions