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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2020-07-09 19:33:43 +0800 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-07-16 10:51:00 +0200 |
| commit | 770a697c45de1b40391c4fc0e6350135563e97a7 (patch) | |
| tree | 1a7d0fc404af2582f7ebb28742ce6c4a585079bc /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 24af105962c8004edb9f5bf84bc587cbb30e52de (diff) | |
MIPS: Loongson64: Load LS7A dtbs
Load correct devicetree according to PRID and PCH type.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions