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authorNitheesh Sekar <quic_nsekar@quicinc.com>2025-05-14 09:52:13 +0400
committerBjorn Andersson <andersson@kernel.org>2025-05-14 20:49:04 +0100
commit18a5bf00a02ca54d51266b861518f2844c4f08d7 (patch)
treeda9782a119bf2109f46c216bb4b4ac8355210ba8 /tools/perf/scripts/python/libxed.py
parent295217420a44403a33c30f99d8337fe7b07eb02b (diff)
arm64: dts: qcom: ipq5018: Add PCIe related nodes
Add phy and controller nodes for a 2-lane Gen2 and a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and one global interrupt. NOTE: the PCIe controller supports gen3, yet the phy is limited to gen2. Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> Signed-off-by: Sricharan R <quic_srichara@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250514-ipq5018-pcie-v10-1-5b42a8eff7ea@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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