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authorVille Syrjälä <ville.syrjala@linux.intel.com>2022-09-07 12:10:46 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2022-09-08 14:20:31 +0300
commite95132ef5d458b3e9d75acfbf4770e8b34de5315 (patch)
tree3e65a462db98ae36ace2a801aae8b10e0cb3b2bf /tools/perf/scripts/python/exported-sql-viewer.py
parentb000abd3b3d2f06e9cc60c19dd4c893cb3531d76 (diff)
drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
Only reassign the pipe's DPLL if it's going through a full .compute_config() cycle. If OTOH it's just getting modeset eg. in order to change cdclk there doesn't seem much point in picking a new DPLL for it. This should also prevent .get_dplls() from seeing a funky port_clock for DP even in cases where the readout produces a non-standard clock and we (for some reason) have decided to not fully recompute the state to remedy the situation. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-7-ville.syrjala@linux.intel.com
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