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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2023-07-12 16:11:53 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-07-25 11:41:09 +0200 |
| commit | fe7297bf011bf6910d76010ba1763daf1286cbf4 (patch) | |
| tree | d8e6809b462b9716ac082313b92e78f27495739c /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 7a98d75c4a63a90e81178170b748512e7a23417d (diff) | |
arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0
The PHY interrupt (INT_N) pin is connected to IRQ0 for ETH0.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230712151153.81965-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions