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| author | Arun R Murthy <arun.r.murthy@intel.com> | 2024-10-11 10:28:25 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2024-11-18 13:32:45 +0530 |
| commit | eb0c1757a36cabb730cde4e045eb52587602504d (patch) | |
| tree | 3eb102a21362c739dc743afd357b2737416516b1 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | af02ee4fb63342c873b747d724cd5ada13c2bde1 (diff) | |
drm/i915/dp: read Aux RD interval just before setting the FFE preset
Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence of
DP2.1a spec.
After reading LANEx_CHANNEL_EQ_DONE, read the FFE presets.
AUX_RD_INTERVAL and then write the new FFE presets.
v4: Read AUX_RD_INTERVAL before get/set TX FFE preset (Jani)
Co-developed-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241011045825.2629469-1-arun.r.murthy@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions