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author | Cezary Rojewski <cezary.rojewski@intel.com> | 2022-03-31 15:52:37 +0200 |
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committer | Mark Brown <broonie@kernel.org> | 2022-04-19 12:03:54 +0100 |
commit | 276b83c807a2bc2a8d9874a92b7fb7811c2df8b2 (patch) | |
tree | 115cdea12cc5878e97fd273dfb2eeea49f590b6f /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 1fba20364318819ecedab2d0f6a68a038f4f47c3 (diff) |
ASoC: Intel: avs: Parse pipeline and module tuples
Shape of a path on DSP side, that is, the number and the layout of its
pipelines and modules is paramount for streaming to be efficient and low
power-consuming. Add parsing helpers to support loading such information
from the topology file.
Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20220331135246.993089-6-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions