diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2020-10-14 12:19:32 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2020-10-15 14:14:32 -0700 |
| commit | 0dac17af0ab4e55b6b18a762141f255d3eea1e37 (patch) | |
| tree | 92d4e33d076720baf28100508830f7ec40beea20 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | b71b477d9414fda42126fd2c55c5e8fa09347433 (diff) | |
drm/i915/dg1: Enable DPLL for DG1
Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id. Although we use
_MG_PLL1_ENABLE/_MG_PLL2_ENABLE these are rather combo phys.
While at it, fix coding style: wrong newlines and use if/else chain
v2: Rewrite original patch from Aditya Swarup based on refactors
upstream
Bspec: 49443, 49206
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-6-lucas.demarchi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions