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| author | Leo (Hanghong) Ma <hanghong.ma@amd.com> | 2019-11-07 16:30:04 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-12-05 16:29:11 -0500 |
| commit | fa11d3c9425354c4b47e40f34d29c5b0949fe4ce (patch) | |
| tree | a36387aa85568403951f437a9bf6df34f2139bda /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 728a5068239d0f50b4346089e30ba744b5954288 (diff) | |
drm/amd/display: Change the delay time before enabling FEC
[why]
DP spec requires 1000 symbols delay between the end of link training
and enabling FEC in the stream. Currently we are using 1 miliseconds
delay which is not accurate.
[how]
One lane RBR should have the maximum time for transmitting 1000 LL
codes which is 6.173 us. So using 7 microseconds delay instead of
1 miliseconds.
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions