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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-06-13 22:45:40 +0900 |
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committer | Boris Brezillon <boris.brezillon@free-electrons.com> | 2017-06-20 09:14:34 +0200 |
commit | f486287d2372422d68768c88fe54e80a48aee8ec (patch) | |
tree | a8fa9ad05bd02af3816c397d36098805e0cd3425 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | fa6134e5457d3177b82b35fa4004505f2571150a (diff) |
mtd: nand: denali: fix bank reset function to detect the number of chips
The nand_scan_ident() iterates over maxchips, and calls nand_reset()
for each. This driver currently passes the maximum number of banks
(=chip selects) supported by the controller as maxchips. So, maxchips
is typically 4 or 8. Usually, less number of NAND chips are connected
to the controller.
This can be a problem for ONFi devices. Now, this driver implements
->setup_data_interface() hook, so nand_setup_data_interface() issues
Set Features (0xEF) command, which waits until the chip returns R/B#
response. If no chip there, we know it never happens, but the driver
still ends up with waiting for a long time. It will finally bail-out
with timeout error and the driver will work with existing chips, but
unnecessary wait will give a bad user experience.
The denali_nand_reset() polls the INTR__RST_COMP and INTR__TIME_OUT
bits, but they are always set even if not NAND chip is connected to
that bank. To know the chip existence, INTR__INT_ACT bit must be
checked; this flag is set only when R/B# is toggled. Since the Reset
(0xFF) command toggles the R/B# pin, this can be used to know the
actual number of chips, and update denali->max_banks.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions