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authorAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>2023-03-01 10:55:18 +0100
committerMatthias Brugger <matthias.bgg@gmail.com>2023-03-30 09:47:08 +0200
commitd434abbb560aae20b31caa34088c3677fe925be6 (patch)
treea4f8e793bc58210f05156da2211fdb4e1d3e43aa /tools/perf/scripts/python/export-to-postgresql.py
parent309460b6260195ae0631c8f15ddb1c23a00b4562 (diff)
arm64: dts: mediatek: mt8195: Add mfg_core_tmp clock to MFG1 domain
Similarly to what can be seen in MT8192, on MT8195 the mfg_core_tmp clock is a mux used to switch between different "safe" (and slower) clock sources for the GPU: this is used during MFGPLL reconfiguration and eventually during idling at very low frequencies. This clock getting turned off means that the GPU will occasionally be unclocked, producing obvious consequences such as system crash or unpredictable behavior: assigning it to the top level MFG power domain will make sure that this stays on at all times during any operation on the MFG domain (only GPU-related transactions). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-15-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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