diff options
| author | Subhash Jadavani <subhashj@codeaurora.org> | 2017-09-27 11:04:40 +0530 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2017-10-30 11:45:58 +0100 |
| commit | c7ccee224d2d551f712752c4a16947f6529d6506 (patch) | |
| tree | 20529cd4df3910eea1b2c4c6d7b12233d66bd3ab /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 6a11fc47f175c8d87018e89cb58e2d36c66534cb (diff) | |
mmc: sdhci-msm: fix issue with power irq
SDCC controller reset (SW_RST) during probe may trigger power irq if
previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
enable the power irq interrupt in GIC (by registering the interrupt
handler), we need to ensure that any pending power irq interrupt status
is acknowledged otherwise power irq interrupt handler would be fired
prematurely.
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions