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| author | Matt Roper <matthew.d.roper@intel.com> | 2022-06-07 17:51:08 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-06-08 07:25:03 -0700 |
| commit | c5cb0002d14b6f7aabaf7d67d0515fe70aea7167 (patch) | |
| tree | 5eb3703ff328d327c3ec8f5a5a699299e980163f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 5821a0bbb4c39960975d29d6b58ae290088db0ed (diff) | |
drm/i915: More PVC+DG2 workarounds
A new PVC+DG2 workaround has appeared recently:
- Wa_16015675438
And a couple existing DG2 workarounds have been extended to PVC:
- Wa_14015795083
- Wa_18018781329
Note that Wa_16015675438 asks us to program a register that is in the
0x2xxx range typically associated with the RCS engine, even though PVC
does not have an RCS. By default the GuC will think we've made a
mistake and throw an exception when it sees this register on a CCS
engine's save/restore list, so we need to pass an extra GuC control flag
to tell it that this is expected and not a problem.
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220608005108.3717895-1-matthew.d.roper@intel.com
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