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| author | Deepak M <m.deepak@intel.com> | 2017-02-17 18:13:30 +0530 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2017-02-28 11:31:17 +0200 |
| commit | b426f985158d9a723ab195258748c0c5e0793a52 (patch) | |
| tree | c40c772e52f19adf3296d361e61ad579e4583402 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 39299838eea1a310b1309b538b80cd00603698fd (diff) | |
drm/i915/glk: Program new MIPI DSI PHY registers for GLK
Program the clk lane and tlpx time count registers
to configure DSI PHY.
v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Program clk lane timing reg same as dphy param reg.
v4: Removed "line over 80 character" warning
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1487335415-14766-3-git-send-email-madhav.chauhan@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions