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| author | Gaurav K Singh <gaurav.k.singh@intel.com> | 2014-12-04 10:58:54 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-12-05 15:29:15 +0100 |
| commit | aa102d286a022fb0f42238c62c2b05cdac12109d (patch) | |
| tree | c7be843c28cf58fe03be10421fa4901125149d8b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 3770f0eec40cb9f1fb7af6453f7bcb420a8a86bc (diff) | |
drm/i915: MIPI Timings related changes for dual link
hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.
v2: Address review comments by Jani
- Used a for loop instead of do-while loop
v3: Used for_each_dsi_port macro instead of for loop
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions