diff options
| author | Manasi Navare <manasi.d.navare@intel.com> | 2018-11-28 12:26:23 -0800 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2018-11-29 12:31:14 -0800 |
| commit | a600622c09ddf7da660ca714d5644ecf270426fc (patch) | |
| tree | e58c920943155996b1c7ed5ae9a1af57c451410d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | a311b0b5d2094029dce2369d686044131e19e006 (diff) | |
drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-12-manasi.d.navare@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions