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authorMatt Roper <matthew.d.roper@intel.com>2022-06-10 16:08:01 -0700
committerMatt Roper <matthew.d.roper@intel.com>2022-06-14 14:52:13 -0700
commit9affc1b87ecba31458567359b5a28b0b08920a24 (patch)
treef24ab92895f54fdf92f54330c10be8129930585c /tools/perf/scripts/python/export-to-postgresql.py
parente0d7371b46c7b47cdf5391717292033365801437 (diff)
drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT()
If we're treating each bit in the EU fuse register as a single EU instead of a pair of EUs, then that also cuts the number of potential EUs per subslice in half. Fixes: 5ac342ef84d7 ("drm/i915/pvc: Add SSEU changes") Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220610230801.459577-1-matthew.d.roper@intel.com
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