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authorPiyush Mehta <piyush.mehta@xilinx.com>2021-02-08 23:33:56 +0530
committerJens Axboe <axboe@kernel.dk>2021-03-12 07:28:29 -0700
commit9a9d3abe24bb6b820e50190147ac880fd0b168f6 (patch)
treeed78ee73cecd33c6aca0bcc75f8e966be5db67f1 /tools/perf/scripts/python/export-to-postgresql.py
parent3c0198c8f30e6e203e050a924aab888f380fe9e3 (diff)
ata: ahci: ceva: Update the driver to support xilinx GT phy
SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy which has 4 GT lanes and can be used by 4 peripherals at a time. SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure the GT lane for the SATA controller, the below sequence is expected. 1. Assert the SATA controller reset. 2. Configure the xilinx GT phy lane for SATA controller (phy_init). 3. De-assert the SATA controller reset. 4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on). The ahci_platform_enable_resources() by default does the phy_init() and phy_power_on() but the default sequence doesn't work with Xilinx platforms. Because of this reason, updated the driver to support the new sequence. Added cevapriv->rst check, for backward compatibility with the older sequence. If the reset controller is not available, then the SATA controller will configure with the older sequences. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
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