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| author | Matthew Gerlach <mgerlach@opensource.altera.com> | 2014-02-03 14:22:59 -0800 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-22 15:17:20 -0500 |
| commit | 7db85dd0828803f44f50ed6953f3f7cb762b830d (patch) | |
| tree | da6edd44622c2966c644b3420ca86dd00096a847 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | e9f9fe35f8940c9a4c5deba091d532e3a02bf78b (diff) | |
ARM: socfpga: dts: add missing clock gates to socfpga.dtsi
The gates for the clocks coming out of the sdram pll
were missing. The change adds the missing nodes to
the device tree.
Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions