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| author | Gaurav K Singh <gaurav.k.singh@intel.com> | 2014-12-04 10:58:52 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-12-05 15:28:45 +0100 |
| commit | 58cf8887c94d8dfe42206af7de57163ce0f46cf2 (patch) | |
| tree | 6563ca1834857d0b292b2ff2d681fc69b5984620 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 4510cd779e5897eeb8691aecbd639bb62ec27d55 (diff) | |
drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.
v2: Address review comments by Jani
- Added wait time for PLL to be locked.
v3: separate patch created for cck read for checking PLL to be locked
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions