diff options
| author | Wenjing Liu <wenjing.liu@amd.com> | 2021-06-14 18:31:21 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-10-28 14:26:17 -0400 |
| commit | 5354b2bd28082032644a644448ce6fa3fb476cbe (patch) | |
| tree | 10525ebe5598790de991aae2db91964b582c9c3d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ed0ffb5dcde95a13bd0208db0b65416e8406699a (diff) | |
drm/amd/display: adopt DP2.0 LT SCR revision 8
[how]
revision 8 SCR requires DP Source to write TPS2 and FFE lane adjustment
in one 5 byte write aux transaction.
It specifies to read aux rd interval value as soon as we turn on TPS1
pattern.
Cc: Wayne Lin <wayne.lin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions