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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-09-19 12:21:18 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-09-21 08:18:02 -0700 |
| commit | 449f87e66df299a1b79567352cba1f5b29421fba (patch) | |
| tree | 0ea0fad93db37c330d8324b01f446861fa3a2e7b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 858c19720c9ab6db003afc9e2ce8b1bfd3c32644 (diff) | |
drm/i915/xe2lpd: Re-order DP AUX regs
The address of CTL and DATA registers for DP AUX were changed in Xe2_LPD:
now they are all in a single range, with CH_A and CH_B coming right after
the USBC instances. Like was done when moving registers to PICA, use
a helper macro to remap the ch passed to an index that can be used to
calculate the right offset.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-12-lucas.demarchi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions